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general description the MAX2082 is the worlds first fully-integrated octal ultrasound transceiver. the device is optimized for high- channel-count, high-performance portable and cart-based ultrasound systems. the easy-to-use transceiver allows the user to achieve high-end 2d and doppler imaging capability using substantially less space and power. the transceiver transmitters are high-performance, 3-level 2a pulsers capable of generating high-voltage pulses up to 105v. the highly compact receiver with t/r switch, lna, input coupling and feedback capacitors, variable gain amplifier (vga), anti-aliasing filter (aaf), analog-to-digital con - verter (adc), and digital highpass filter (hpf) achieves an ultra-low noise figure with r s = r in = 200 at a very low 131mw per-channel power dissipation at 50msps. the receive channel has been optimized for second harmonic imaging with -66dbfs second harmonic distor - tion performance at f rf = 5mhz over the full gain range. the full receive channel exhibits an exceptional 76dbfs snr at 5mhz with a 2mhz bandwidth. separate mixers for each channel are made avail - able for optimal cwd sensitivity yielding an impressive 149dbc/hz dynamic range per channel at 1khz offset from the 1.25mhz carrier. the MAX2082 octal ultrasound front-end is available in a small 10mm x 23mm csbga package and is specified over a 0c to +70c temperature range. beneits and features minimizes pcb area and design cost ? 8 full channels of hv pulser, t/r-switch, lna input and feedback coupling caps, lna, vga, aaf, cwd mixers, 12-bit adc, and digital hpf in a small 10mm x 23mm csbga package integrated hv pulser for simpler system design ? high-voltage 3 level pulsers (up to 105v) with active return to zero and internal power-supply drivers for reduced external components ? programmable pulser current capability from 0.5a to 2a for reduced power consumption in lower voltage transmit modes like cwd ? extremely low propagation delay pulsers (18ns) with excellent rise and fall matching for excellent thd2 performance (-43dbc at 5mhz) integrated high-performance receiver improves system sensitivity ? ultra-low full-channel receiver noise figure of 2.8db at r in = r s = 200 (without t/r switch) ? high dynamic range receiver with 76dbfs snr at f in = 5mhz and 2mhz bandwidth ? ultra-low power receiver (131mw per channel) applications ultrasound imaging ordering information appears at end of data sheet. MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer 19-6601; rev 0; 9/14 evaluation kit available downloaded from: http:///
MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 2 out1+ b27 out1+ out1- b28 out1- out2+ c27 out2+ out2- c28 out2- out3+ d27 out3+ out3- d28 out3- out4+ e27 out4+ out4- e28 out4- out5+ h27 out5+ out5- h28 out5- out6+ j27 out6+ out6- j28 out6- out7+ k27 out7+ out7- k28 out7- out8+ l27 out8+ out8- l28 out8- clkout+ f27 clkout+ clkout- f28 clkout- frame+ g27 frame+ frame- g28 frame- f26 ovdd g26 ovdd 100nf ovdd a28 ovdd 100nf ovdd shdn b26 shdn cwd a26 cwd b25 i.c. a25 refio 100nf a24 avdd loon loon avdd a23b23 b24 n.c. 100nf avdd lo- lo- b22 lo+ lo+ a22 cq- b21 cq+ a21 ci- b20 ci+ a20 120 ? 120 ? 120 ? 120 ? 11v v cc5 a19 b19 100nf v cc5 v cc3 100nf v cc3 m28 ovdd 100nf ovdd cs m27 cs sclk m26 sclk l26 m24 l24 avdd m23l23 m22 l22 m21 l21 l20 m19 m20 sdio sdio clkin- clkin- clkin+ clkin+ avdd 100nf avdd 100nf v cc3 100nf 100nf v cc3 v cc3 v g+ v g+ v g- v g- v ref v ref v cc5 v cc5 100nf v cc5 100nf l19 v cc5 b1 c1 d1 e1 h1 j1 k1 l1 tr1 tr2 tr3 tr4 tr5 tr6 tr7 tr8 b2 c2 d2 e2 a2 b3 c3 d3 e3 a3 +hv0 tvgpa a4 tvgna b4 10v, 1f -hv0 10v, 1f tvppa tvnna tvcc a5 b5 tvcc tvee tvee a1 a18a17 a16 a15 a14 a13 a27 b18b17 b15 b14 b13 b10 c8c7 c9 c6 c5 c4 c18c17 c19 c15 c14 c13 c12 c11 c10 c26 c25 c24 c23 c22 c21 c20 d8d7 d9 d6 d5 d4 d18d17 d19 d15 d14 d13 d12 d11 d10 d26 d25 d24 d23 d22 d21 d20 e8e7 e9 e6 e5 e4 e18e17 e19 e15 e14 e13 e12 e11 e10 e26 e25 e24 e23 e22 e21 e20 f8f7 f9 f6 f5 f4 f3 f2 f1 f17 f19 f16 f15 f14 f13 f12 f11 f10 f25 f24 f23 f22 f21 f20 g8g7 g9 g6 g5 g4 g3 g2 g1 g17 g19 g16 g15 g14 g13 g12 g11 g10 g25 g24 g23 g22 g21 g20 h8h7 h9 h6 h5 h4 h18h17 h19 h15 h14 h13 h12 h11 h10 h26 h25 h24 h23 h22 h21 h20 j8j7 j9 j6 j5 j4 j18j17 j19 j15 j14 j13 j12 j11 j10 j26 j25 j24 j23 j22 j21 j20 k8k7 k9 k6 k5 k4 k18k17 k19 k15 k14 k13 k12 k11 k10 k26 k25 k24 k23 k22 k21 k20 l18l17 l15 l14 l13 l25 m1 m18m17 m16 m15 m14 m13 m25 tinn2 tinn2 b7 tinp1 tinp1 a6 tinn1 b6 tinn1 tinp3 tinp3 a8 tinn3 tinn3 b8 tinp2 a7 tinp2 tmode1 tmode1 a11 tinp4 tinp4 a9 tinn4 b9 tinn4 tcc0 tcc0 b12 tcc1 tcc1 a12 tmode0 b11 tmode0 tinn6 tinn6 l7 tinp5 tinp5 m6 tinn5 l6 tinn5 tinp7 tinp7 m8 tinn7 tinn7 l8 tinp6 m7 tinp6 tthp l11 tinp8 tinp8 m9 tinn8 l9 tinn8 tclk- l12 tclk+ tclk+ m12 tsync m11 tsync tclk- ten l10 ten tthp ag f18 g18 ag e16 inb4 d16 inb3 c16 inb2 b16 inb1 33h 33h 33h 33h optional h16 inb5 j16 inb6 k16 inb7 l16 inb8 33h 33h 33h 33h optional tvdd m10 tvdd tvdd a10 tvdd l2 k2 j2 h2 m2 l3 k3 j3 h3 m3 +hv0 tvgpb m4 tvgnb l4 10v, 1mf -hv0 10v, 1mf tvppb tvnnb tvcc m5 l5 tvcc tvee tvee gnd bumps typical application circuit downloaded from: http:///
MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 3 table of contents general description ............................................................................ 1 benefits and features .......................................................................... 1 applications .................................................................................. 1 typical application circuit ....................................................................... 2 absolute maximum ratings ...................................................................... 8 package thermal characteristics ................................................................. 8 octal ultrasound front-end specifications .......................................................... 8 dc electrical characteristicst/r switch and transmitter ............................................. 8 ac electrical characteristicst/r switch and transmitter ............................................ 15 dc electrical characteristicslna, vga, adc (cwd beamformer off) ................................. 17 ac electrical characteristicsvga mode (cwd beamformer off) ..................................... 18 dc electrical characteristicscwd mode (vga, aaf, and adc of f) .................................. 21 ac electrical characteristicscwd mode (vga, aaf, and adc off ) .................................. 22 electrical characteristicsafe clock and timing ................................................. 24 timing diagrams ............................................................................. 26 typical operating characteristics ................................................................ 31 bump configuration ........................................................................... 37 bump description ............................................................................. 38 functional diagram ........................................................................... 42 detailed description ........................................................................... 43 transmit pulser .............................................................................. 43 modes of operation .................................................. ....................... 43 shutdown mode (tmode0, tmode1 = 00) ................................................... . 43 octal 3 level mode (tmode0, tmode1 = 10) ................................................. 43 disable transmit mode (tmode0, tmode1 = 11) .............................................. 43 current capability selection ................................................... ................ 43 sync feature ................................................... ............................ 44 t/r switch and control ................................................... .................... 44 grass clipping diodes ................................................... .................... 44 active damp circuit ................................................... ....................... 45 independent (floating) power-supply enable (ten) ................................................ 45 thermal protection ................................................... ....................... 45 analog front end (afe) ........................................................................ 45 modes of operation .................................................. ....................... 45 low-noise amplifier (lna) ................................................... ................. 45 variable-gain amplifier (vga) ................................................... .............. 45 overload recovery ................................................... ....................... 46 octal continuous-wave (cw) mixer ................................................... .......... 46 downloaded from: http:///
MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 4 table of contents (continued) cw mixer output summation ................................................... ............... 46 lo phase select ................................................... ......................... 46 vga and cw mixer operation ................................................... .............. 46 external voltage reference ................................................... ................ 46 adc clock input ................................................... ......................... 46 power-down and low-power mode ................................................... .......... 48 programmable, digital highpass 2-pole filter ................................................... .. 48 digital highpass filter characteristics ................................................... ...... 48 system timing requirements ................................................... ............... 54 clock output (clkout+, clkout-) ................................................... ....... 54 frame-alignment output (frame+, frame-) .................................................. 55 serial-output data (out_+, out_-) ................................................... ....... 55 differential lvds digital outputs ................................................... ............ 55 output driver level tests .................................................. ................ 56 data output test patterns ................................................... ............... 56 power management ................................................... ...................... 56 power-on and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 power-down and low-power (nap) mode and channel selection ................................... 56 3-wire serial peripheral interface (spi) ................................................... ....... 57 spi communication format ................................................... .............. 57 output clock phase ................................................... .................... 57 custom test pattern ................................................... ................... 61 clock input termination ................................................... ................. 64 cw doppler mode control ................................................... ................. 67 soft reset ................................................... .............................. 68 afe programming and data transfer ................................................... ........ 68 cwd beamformer programming and clocking .................................................. .. 68 applications information ........................................................................ 69 layout concerns ................................................... ......................... 69 power-supply sequencing ................................................... ................. 69 ordering information .......................................................................... 70 chip information .............................................................................. 70 package information .......................................................................... 70 revision history .............................................................................. 71 downloaded from: http:///
MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 5 list of figures figure 1. cwd loon lo turn-on/turn-off setup time .............................................. 26 figure 2. hv burst test (three levels) ............................................................ 26 figure 3. propagation delay timing .............................................................. 27 figure 4. output rise/fall timing ................................................................ 27 figure 5. t/r switch turn-on/off time ............................................................ 28 figure 6. bandwidth ........................................................................... 29 figure 7. jitter timing .......................................................................... 30 figure 8. simplified clock input schematic ......................................................... 45 figure 9. cwd analog front-end beamformer simplified block diagram ................................. 47 figure 10. cwd output beamforming example ..................................................... 47 figure 11. simplified clock input schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 12. two-stage digital highpass filter with 1-stage multiplier ..................................... 49 figure 13. digital hpf magnitude frequency response (1 stage) ....................................... 51 figure 15. digital hpf phase response (1 stage) ................................................... 51 figure 14. digital hpf magnitude frequency response (1 stag e) at corner frequency ...................... 51 figure 16. digital hpf group-delay frequency response (1 st age) ..................................... 51 figure 17. digital hpf impulse-time response (1 stage) ............................................. 52 figure 19. digital hpf magnitude frequency response (2 stage) ....................................... 52 figure 18. digital hpf impulse-time response detailed plot (1 stage) .................................. 52 figure 20. digital hpf magnitude frequency response (2 stag e) at corner frequency ..................... 52 figure 21. digital hpf phase response (2 stage) ................................................... 53 figure 23. digital hpf impulse-time response (2 stage) ............................................. 53 figure 22. digital hpf group-delay frequency response (2 st age) ..................................... 53 figure 24. digital hpf impulse-time response detailed plot (2 stage) .................................. 53 figure 25. digital hpf gain vs. filter coefficient .................................................... 54 figure 26. adc timing (overall) ................................................................. 54 figure 27. adc timing (detail) .................................................................. 55 figure 28. serial output detailed timing diagram ................................................... 55 figure 29. spi timing diagram .................................................................. 58 figure 30. output clock phase .................................................................. 61 figure 31. ultrasound-specific imd3 .............................................................. 69 downloaded from: http:///
MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 6 list of tables table 1. transmit pulser operating modes and truth table ............................................ 44 table 2. transmit pulser output current ........................................................... 44 table 3. digital filter cutoff-frequency setting ...................................................... 49 table 4. gain-compensation settings for different filter cu toff-frequency settings ........................ 50 table 5. user-programmable adc control registers ................................................. 59 table 6. pll sampling rate and power management (00h) ............................................ 59 table 7. pll frequency-control settings (00h[6:4]) .................................................. 59 table 8. power-management programming ........................................................ 60 table 9. output data format and test pattern/digital hpf sele ct (01h) .................................. 60 table 10. lvds output data format programming (01h[1:0]) ........................................... 61 table 11. test pattern programming and digital highpass filt er selection ................................ 61 table 12. pseudorandom data test pattern ........................................................ 62 table 13. lvds output driver level (02h) .......................................................... 62 table 14. test data (out_) level programming ..................................................... 62 table 15. test clkout_ level programming ....................................................... 62 table 16. test frame level programming ......................................................... 62 table 17. lvds output common-mode voltage adjustment ........................................... 62 table 18. lvds output driver management (03h) ................................................... 63 table 19. lvds output drive current configuration .................................................. 63 table 20. lvds output driver internal termination configur ation ....................................... 63 table 21. clkin termination control (04h) ......................................................... 63 table 22. channel power management: shdn0 (05h) ................................................ 64 table 23. channel power management: shdn1 (06h) ................................................ 64 table 24. digital highpass filter control coefficients (07 h; if test_data 01[4]) = 0) ....................... 64 table 25. digital highpass filter configuration ...................................................... 64 table 26. custom test pattern 1 (07h; if test_data 01[4]) = 1) ........................................ 64 table 27. digital highpass filter attenuation (08h; if test_ data 01[4]) = 0) .............................. 65 table 28. digital highpass filter attenuation ........................................................ 65 table 29. custom test pattern 2 (08h; if test_data 01[4]) = 1) ........................................ 65 table 30. custom test pattern 3 (09h) ............................................................ 65 table 31. afe settings (0ah) .................................................................... 65 downloaded from: http:///
MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 7 list of tables (continued) table 32. afe input impedance and lna gain control ............................................... 65 table 33. afe aaf filter bandwidth control ....................................................... 66 table 34. cwd power mode .................................................................... 66 table 35. vga output clamp control ............................................................. 66 table 36. cw beamformer 1 (0bh) ............................................................... 66 table 37. cw beamformer 2 (0ch) ............................................................... 66 table 38. cw beamformer 3 (0dh) ............................................................... 66 table 39. cw beamformer 4 (0eh) ............................................................... 66 table 40. cw beamformer 5 (0fh) ............................................................... 67 table 41. phase rotation bit weight .............................................................. 67 table 42. phase rotation summary .............................................................. 67 table 43. special function register (10h) .......................................................... 67 table 44. status byte (reads from 10h) ........................................................... 68 table 45. spi commands (writes to 10h) .......................................................... 68 downloaded from: http:///
v cc5 , v cc3 to gnd ............................................. -0.3v to +5.5v avdd, ovdd to gnd .......................................... -0.3v to +2.1v v cc5 - v cc3 to gnd ...................................................... > -0.3v v ref , gc+/- to gnd ................................. -0.3 to (v cc3 + 0.3v) ci+/-, cq+/- to gnd .............................................. -0.3v to +13v ag, lo+/- to gnd ..................................... -0.3 to (v cc5 + 0.3v) inb_ current .............................................................. 20ma dc refio, clkin+/-, loon to gnd .............. -0.3v to the lower of (v avdd + 0.3v) and 2.1v out+/-, sdio, sclk, cs, clkout+/-, frame+/-, shdn, cwd to gnd -0.3v to the lower of (v ovdd + 0.3v) and 2.1v tvdd, tvcc to gnd ........................................... -0.3v to +5.6v tvee to gnd ....................................................... -5.6v to +0.3v tvnna, tvnnb to gnd ..................................... -110v to +0.3v tvppa, tvppb to gnd ...................................... -0.3v to +110v tr_ output voltage range ........................... v tvnn_ to v tvpp_ tinp_, tinn_, tcc_, tsync, ten, thp to gnd ...................................................... -0.3v to +5.6v tmode_, tclk+, tclk-, to gnd ....... -0.3v to (v tvcc + 0.3v) tvgpa, tvgpb to gnd ........................... max[(v tvpp_ - 5.6v), (v tvee + 0.6v)] to (v tvpp_ + 0.3v) tvgna, tvgnb to gnd ....................... (v tvnn_ C 0.3v) to min [(v tvcc + 0.6v), (v tvnn_ + 5.6v)] tvpp, tvnn, ci+/-, cq+/-, v cc5 , tvcc, tvee, tvdd, v cc3 , avdd/ovdd, v ref , analog and digital control signals must be applied in this order continuous current (ingp_, ingn_) ............................. 100ma continuous power dissipation (t a = +70c) csbga (derate 28.6mw/c above +70c) ............... 3500mw operating ambient temperature range (note 1) .. 0c to +70c junction temperature ...................................................... +150c storage temperature range ............................ -40c to +150c soldering temperature (reflow) ....................................... +260c junction-to-ambient thermal resistance ( ja ) .......... 23c/w junction-to-case thermal resistance ( jc ) .............. 5.2c/w (note 2) (v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, v tvdd = 3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v gnd = 0v, shdn = 0, r in = 200, high lna gain. t a = 0c to +70c. connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_, ten = 0. typical values are at v cc3 = 3.3v, v cc5 = 4.75v, v avdd = 1.8v, v ovdd = 1.8v, t a = +25c, unless otherwise noted.) ( note 3) parameter symbol conditions min typ max units power supplies (tvdd, tvcc, tvee, tvpp_, tvnn_) logic supply voltage v tvdd 1.7 3 5.25 v positive drive supply voltage v tvcc 4.9 5 5.1 v negative drive supply voltage v tvee -5.1 -5 -4.9 v high-side supply voltage v tvpp_ 0 +105 v low-side supply voltage v tvnn_ -105 0 v external floating power-supply current from tv gn _ i tvgn_ ten = high (note 4), v tvgn - v tvnn = +5v 14 ma external floating power-supply current from tv gp_ i tvgp_ ten = high (note 4) v tvpp - v tvgp = +5v 18 ma MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 8 note 1: t c is the temperature on the bump of the package. t a is the ambient temperature of the device and pcb. note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics dc electrical characteristicst/r switch and transmitter octal ultrasound front-end speciications downloaded from: http:///
(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, v tvdd = 3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v gnd = 0v, shdn = 0, r in = 200, high lna gain. t a = 0c to +70c. connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_, ten = 0. typical values are at v cc3 = 3.3v, v cc5 = 4.75v, v avdd = 1.8v, v ovdd = 1.8v, t a = +25c, unless otherwise noted.) ( note 3) parameter symbol conditions min typ max units logic inputs/outputs (tinn_, tinp_, tmode_, tsync, tcc_, ten) low-level input threshold v il 0.2 x v tvdd v high-level input threshold v ih 0.8 x v tvdd v logic-input capacitance c in 5 pf logic-input leakage (all inputs except ten) i in v in = 0v or v tvdd -1 0 +1 a ten pulldown resistance r ten 6.7 10 14 k w thp low-level output voltage v ol pullup resistor to tvdd (r pullup = 1k w ) 0.1 x v tvdd v clock inputs (tclk+, tclk-)differential mode differential clock input voltage range v tclkd 0.2 2 v p-p common-mode voltage v tclkcm v tvcc /2 v common-mode voltage range v cl v tvcc /2 - 0.45 v tvcc /2 + 0.45 v input resistance r tclk+, r tclk- differential 6.7 k w common mode 21.5 k w input capacitance c tclk+ , c tclk- capacitance to gnd (each input) 5 pf clock inputs (tclk+, tclk-)single-ended mode (vtclk- < 0.1v) low-level input v il tclk+ 0.2 x v tvdd v high-level input v ih tclk+ 0.8 x v tvdd v single-ended mode selection threshold low v il tclk- 0.1 v single-ended mode selection threshold high v ih tclk- 1 v input capacitance (tclk_) c tclk_ 5 pf logic-input leakage (tclk+) i tclk+ v tclk+ = 0v or v tvdd -1 0 +1 a pullup current (tclk-) i tclk- v tclk- = 0v 120 180 a MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 9 dc electrical characteristicst/r switch and transmitter (continued) downloaded from: http:///
(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, v tvdd = 3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v gnd = 0v, shdn = 0, r in = 200, high lna gain. t a = 0c to +70c. connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_, ten = 0. typical values are at v cc3 = 3.3v, v cc5 = 4.75v, v avdd = 1.8v, v ovdd = 1.8v, t a = +25c, unless otherwise noted.) ( note 3) parameter symbol conditions min typ max units supply currentshutdown mode (tmode0 = low, tmode1 = low) tvdd supply current i tvdd all inputs connected to gnd or tvdd 3 a tvcc supply current i tvcc all inputs connected to gnd or tvdd 22 a tvee supply current i tvee all inputs connected to gnd or tvdd 13 a tvpp_ supply current i tvpp_ all inputs connected to gnd or tvdd 10 a tvnn_ supply current i tvnn_ all inputs connected to gnd or tvdd 10 a supply currentdisable mode (tmode0 = high, tmode1 = high) tvdd supply current i tvddq all inputs connected to gnd or tvdd transparent or single-ended clock mode 1.7 3 a differential clock mode, v tclkd = 0.2v 110 190 tvee supply current i tveeq tinn_ = tinp_ = gnd 0.27 0.4 ma tinn_ = tinp_ = v tvdd 9.9 13.3 tvcc supply current i tvccq tinn_ = tinp_ = gnd 0.5 0.75 ma tinn_ = tinp_ = v tvdd 10.1 13.6 tvcc supply current increase in clocked mode i tvcc differential clock mode 3.5 5 ma tvnn_ total supply current (quiescent mode) i tvnnq_ all inputs connected to gnd or tvdd 200 305 a tvpp_ total supply current (quiescent mode) i tvppq_ all inputs connected to gnd or tvdd 220 340 a total power dissipation per channel (disable mode) p pdis1 t/r switch off, damp off (transparent mode) 5.7 mw p pdis2 tinn_ = tinp_ = v tvdd 17.8 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 10 dc electrical characteristicst/r switch and transmitter (continued) downloaded from: http:///
(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, v tvdd = 3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v gnd = 0v, shdn = 0, r in = 200, high lna gain. t a = 0c to +70c. connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_, ten = 0. typical values are at v cc3 = 3.3v, v cc5 = 4.75v, v avdd = 1.8v, v ovdd = 1.8v, t a = +25c, unless otherwise noted.) ( note 3) parameter symbol conditions min typ max units supply currentoctal three-level mode, no load (tmode0 = high, tmode1 = low) tvdd supply current (quiescent mode) i tvdd all inputs connected to gnd or tvdd transparent or single-ended clock mode 1.7 3 a differential clock mode, v tclkd = 0.2v 110 190 tvee supply current (quiescent mode) i tveeq tinn_ = tinp_ = gnd 0.27 0.4 ma tinn_ = tinp_ = v tvdd 9.9 13.3 tvcc supply current (quiescent mode) i tvccq tinn_ = tinp_ = gnd 0.5 0.75 ma tinn_ = tinp_ = v tvdd 10.1 13.6 tvcc supply current increase in clocked mode i tvcc differential clock mode 3.5 5 ma tvnn_ total supply current (quiescent mode) i tvnnq_ all inputs connected to gnd or tvdd 200 305 a tvpp_ total supply current (quiescent mode) i tvppq_ all inputs connected to gnd or tvdd 220 340 a total power dissipation per channel (quiescent mode) p pdis1 t/r switch off, damp off (transparent mode) 5.7 mw p pdis2 tinn_ = tinp_ = v tvdd (transparent mode) 17.8 tvdd supply current i tvdd1 cw doppler (note 5), transparent or single-ended clock mode 2.2 3.3 ma i tvdd2 b mode (note 6), transparent or single-ended clock mode, figure 2 10 20 a tvee supply current i tvee1 8 channels switching, cw doppler (note 5), tcc0 = high, tcc1 = high 65 92 ma i tvee2 8 channels switching, b mode (note 6), figure 2, tcc0 = low, tcc1 = low 10.3 15.2 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 11 dc electrical characteristicst/r switch and transmitter (continued) downloaded from: http:///
(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, v tvdd = 3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v gnd = 0v, shdn = 0, r in = 200, high lna gain. t a = 0c to +70c. connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_, ten = 0. typical values are at v cc3 = 3.3v, v cc5 = 4.75v, v avdd = 1.8v, v ovdd = 1.8v, t a = +25c, unless otherwise noted.) ( note 3) parameter symbol conditions min typ max units tvcc supply current i tvtcc1 8 channels switching, cw doppler (note 5), tcc0 = high, tcc1 = high 45 60 ma i tvcc2 8 channels switching, b mode (note 6), figure 2, tcc0 = low, tcc1 = low 10.5 15.4 tvdd supply current increase in clocked mode i tvdd differential clock mode 1.8 ma tvcc supply current increase in clocked mode i tvcc differential clock mode 3.8 ma tvnn_ supply current i tvnn1 8 channels switching, cw doppler (note 5) tcc0 = high, tcc1 = high, r l = 1k w , c l = 200pf 157 200 ma i tvnn2 8 channels switching, b mode (note 7), figure 2, tcc0 = low, tcc1 = low, r l = 1k w , c l = 200pf 1.7 2.8 tvpp_ supply current i tvpp1 8 channels switching, cw doppler (note 5) tcc0 = high, tcc1 = high, r l = 1k w , c l = 200pf 186 230 ma i tvpp2 8 channels switching, b mode (note 6), figure 2, tcc0 = low, tcc1 = low, r l = 1k w , c l = 200pf 2.7 4.5 power dissipation per channel (octal three-level mode) pd cw 1 channel switching, cw doppler (note 5) 285 mw pd pw 1 channels switching, b mode (note 6), figure 2, tcc0 = low, tcc1 = low, r l = 1k w , c l = 200pf 68 supply currentoctal three-level mode, no load (tmode0 = high, tmode1 = low, ten = high, v tvpp_ - v tvgp_ = +5v, v tvgn_ - v tvnn_ = +5v) tvee supply current (quiescent mode) i tveeq_ 25 a tvcc supply current (quiescent mode) i tvccq_ all inputs connected to gnd 280 a MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 12 dc electrical characteristicst/r switch and transmitter (continued) downloaded from: http:///
(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, v tvdd = 3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v gnd = 0v, shdn = 0, r in = 200, high lna gain. t a = 0c to +70c. connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_, ten = 0. typical values are at v cc3 = 3.3v, v cc5 = 4.75v, v avdd = 1.8v, v ovdd = 1.8v, t a = +25c, unless otherwise noted.) ( note 3) parameter symbol conditions min typ max units tvnn_ supply current (quiescent mode) i tvnnq_ all inputs connected to gnd 40 a tvpp_ supply current (quiescent mode) i tvppq_ all inputs connected to gnd 40 a output stage tvnna , tvnnb connected low- side output impedance r ols i out_ = -50ma tcc0 = low, tcc1 = low 8.5 w tcc0 = high, tcc1 = low 10 tcc0 = low, tcc1 = high 13.5 tcc0 = high, tcc1 = high 26 46 tvppa , tvppb connected high- side output impedance r ohs i out_ = +50ma tcc0 = low, tcc1 = low 9 w tcc0 = high, tcc1 = low 10.5 tcc0 = low, tcc1 = high 14.5 tcc0 = high, tcc1 = high 27 52 clamp nfet output impedance r ong i out_ = -50ma, 13.5 w clamp pfet output impedance r opg i out_ = +50ma 13.5 w active damp output impedance r damp before grass-clipping diode 500 w tvnna , tvnnb connected low- side output current i ols v ds = 100v tcc0 = low, tcc1 = low 2.0 a tcc0 = high, tcc1 = low 1.5 tcc0 = low, tcc1 = high 1.0 tcc0 = high, tcc1 = high 0.5 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 13 dc electrical characteristicst/r switch and transmitter (continued) downloaded from: http:///
(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, v tvdd = 3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v gnd = 0v, shdn = 0, r in = 200, high lna gain. t a = 0c to +70c. connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_, ten = 0. typical values are at v cc3 = 3.3v, v cc5 = 4.75v, v avdd = 1.8v, v ovdd = 1.8v, t a = +25c, unless otherwise noted.) ( note 3) parameter symbol conditions min typ max units tvppa , tvppb connected high- side output current i ohs v ds = 100v tcc0 = low, tcc1 = low 2.0 a tcc0 = high, tcc1 = low 1.5 tcc0 = low, tcc1 = high 1.0 tcc0 = high, tcc1 = high 0.5 gnd-connected nfet output current i ong v ds = 100v 1 a gnd-connected pfet output current i opg v ds = 100v 1 a diode voltage drop (blocking diode and grass-clipping diode) v drop i out_ = 50ma 1.7 v grass-clipping diode reverse capacitance c rev 2.5 pf tr_ equivalent large-signal shunt capacitance c hs 200v p-p signal 80 pf t/r switch on-impedance r on f = 5mhz,v tr = 0v 11.5 t/r switch off-impedance r off 1 m t/r switch output offset tr off inb_, tr_ unconnected, v tvcc = +5v, v tvee = -5v -40 +40 mv thermal shutdown thermal-shutdown threshold t sdn temperature rising +145 c thermal-shutdown hysteresis t hys 20 c MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 14 dc electrical characteristicst/r switch and transmitter (continued) downloaded from: http:///
(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, v tvdd = 3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v gnd = 0v, shdn = 0, r in = 200, high lna gain. t a = 0c to +70c. connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_, ten = 0, tcc0 = 0, tcc1 = 0, rl = 1k?, c l = 200pf, unless otherwise noted. typical values are at v cc3 = 3.3v, v cc5 = 4.75v, v avdd = 1.8v, v ovdd = 1.8v, t a = +25c, unless otherwise noted.) parameter symbol conditions min typ max units logic input to output rise propagation delay t plh from 50% tinp_/tinn_ (transparent mode) to 10% out_ transition swing, figure 3 18 ns logic input to output fall propagation delay t phl from 50% tinp_/tinn_ (transparent mode) to 10% out_ transition swing, figure 3 18 ns logic input to output rise to gnd propagation delay t pl0 from 50% tinp_/tinn_ (transparent mode) to 10% out_ transition swing, figure 3 18 ns logic input to output fall to gnd propagation delay t ph0 from 50% tinp_/tinn_ (transparent mode) to 10% out_ transition swing, figure 3 18 ns tr_ fall time (v tvppa to v tvnna , v tvppb to v tvnnb ) t fpn figure 4 30 ns tr_ rise time (v tvnna to v tvppa , v tvnnb to v tvppb ) t rnp figure 4 30 ns tr_ rise time (gnd to v tvppa , gnd to v tvppb ) t r0p figure 4 15 ns tr_ fall time (gnd to v tvnna , gnd to v tvnnb ) t f0n figure 4 15 ns tr_ rise time (v tvnna to gnd , v tvnnb to gnd) t rn0 figure 4 21 ns tr_ fall time (v tvppa to gnd , v tvppb to gnd) t fp0 figure 4 21 ns t/r switch turn-on time t ontrsw figure 5 0.65 1.2 s t/r switch turn-off time t offtrsw figure 5 (note 8) 0.02 0.1 s output enable time (shutdown mode to normal operation) t en1 100 s output disable time (normal operation to shutdown mode) t dis1 10 s output enable time (transmit disable mode to normal operation) t en2 52 ns output disable time (normal operation to transmit disable mode) t dis2 65 ns MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 15 ac electrical characteristicst/r switch and transmitter downloaded from: http:///
(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, v tvdd = 3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v gnd = 0v, shdn = 0, r in = 200, high lna gain. t a = 0c to +70c. connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_, ten = 0. typical values are at v cc3 = 3.3v, v cc5 = 4.75v, v avdd = 1.8v, v ovdd = 1.8v, t a = +25c, unless otherwise noted.) ( note 3) parameter symbol conditions min typ max units output enable time (normal operation to sync mode) t en3 4 s output disable time (sync mode to normal operation) t dis3 500 ns tclk_ frequency f tclk_ v tvdd = 2.5v 200 mhz input setup time (tinn_, tinp_) t setup v tvdd = 2.5v 2 ns input hold time (tinn_, tinp_) t hold v tvdd = 2.5v 0.8 ns second-harmonic distortion (low voltage) thd2lv f out_ = 5mhz, v tvppa = -v tvnna = +5v, v tvppb = -v tvnnb = +5v, square wave (all modes) -40 dbc second-harmonic distortion (high voltage) thd2hv f out_ = 5mhz, v tvppa = -v tvnna = +100v, v tvppb = -v tvnnb = +100v, square wave (all modes) -43 dbc pulse cancellation pc1 f out_ = 5mhz, v tvppa = -v tvnna = +100v, v tvppb = -v tvnnb = +100v, 2 periods, all harmonics of the summed signed with respect to the carrier -40 dbc pc2 f out_ = 5mhz, v tvppa = -v tvnna = +100v, v tvppb = -v tvnnb = +100v, 2 periods, [(v 0 + v 180 ) rms / (2 x v 0rms )] db -40 pulser bandwidth bw v tvppa = +60v, v tvnna = -60v, figure 6 20 mhz rms output jitter t j f out_ = 5mhz, v tvppa = -v tvnna = +5v, v tvppb = -v tvnnb = +5v, both in clocked mode or transparent mode, figure 7 6.25 ps t/r switch harmonic distortion thd trsw r load = 200 w , v signal = 100mv p-p -50 db t/r switch turn-on/off voltage spike v spike r load = 1k w at both sides of t/r switch 50 mv crosstalk ct f = 5mhz, adjacent channels, r ib__ = 200 w -51 db MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 16 ac electrical characteristicst/r switch and transmitter (continued) downloaded from: http:///
(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, v gnd = 0v, t a = 0c to +70c, shdn = 0, cwd = 0, loon = 0, tmode1 = 0, tmode0 = 1, tcc1 = tcc0 = 0, thp = 1, tsync = 0, ten = 0, tinp_ = tinn_ = 1, no tclk_, f rf = 5mhz, 50mv p-p , adc f clk = 50msps, digital hpf set to 60/64, two poles, 15/16 digital gain, v gc+ - v gc- = -3v (minimum gain), high lna gain. connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_. typical values are at v tvdd = 3.3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = 1.8v, v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25c, unless otherwise noted.) ( note 3) parameter symbol conditions min typ max units 3.3v supply voltage v cc3 v cc3 pins 3.13 3.3 3.47 v 5v supply voltage v cc5 v cc5 pins 4.5 4.75 5.25 v 1.8v supply voltage v tcc1.8 avdd and ovdd pins 1.7 1.8 1.9 v external reference voltage range v ref (note 9) 2.475 2.525 v external reference current total current into the v ref pin 5 m a 3v supply current per channel i cc3 total i divided by 8, v gc+ - v gc- = -0.4v 9.5 16 ma 11v supply current per channel i cc11 total i divided by 8 0 ma 5v supply current per channel i cc5 total i divided by 8 6.4 9 ma 1.8v supply current per channel i tcc1.8 total i divided by 8, avdd + ovdd 32 37.9 ma total i divided by 8, avdd 20 22.8 ma total i divided by 8, ovdd 12 15.1 ma dc power per channel p_nm v gc+ - v gc- = -0.4v 131 mw differential analog control voltage range vgain_rang v gc+ - v gc- 3 v 5v supply nap current i _np_5v_tot shdn = 1, nap mode (all 8 channels) 30 ma 3v supply nap current i _np_3v_tot shdn = 1, nap mode (all 8 channels) 0.035 ma 1.8v supply nap current shdn = 1, nap mode (all 8 channels) 40 ma 5v supply power-down current i _pd_5v_tot shdn = 1, power-down mode (all 8 channels) 1 a 3v supply power-down current i _pd_3v_tot shdn = 1, power-down mode (all 8 channels) 1 a 1.8v supply power-down current shdn = 1, power-down mode (all 8 channels) 0.38 ma common-mode voltage for differential analog control v gain_comm (v gc+ - v gc- )/2 1.65 5% v source/sink current for gain control pins i _gc_ per pin 1.6 m a MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 17 dc electrical characteristicslna, vga, adc (cwd beamformer off) downloaded from: http:///
(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0c to +70c, v gnd = 0v, shdn = 0, cwd = 0, loon = 0, tmode1 = 0, tmode0 = 1, tcc1 = tcc0 = 0, thp = 1, tsync = 0, ten = 0, tinp_ = tinn_ = 1, no tclk_, f rf = 5mhz, 50mv p-p , adc f clk = 50msps, digital hpf set to 60/64, two poles, 15/16 digital gain, v gc+ - v gc- = -3v (mini - mum gain), high lna gain, connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_. typical values are at v tvdd = 3.3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25c, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units adc resolution 12 bits minimum adc sample rate 25 msps maximum adc sample rate 50 msps mode-select response time (note 7) cwd stepped from 0 to 1, dc stable within 10% 1 s cwd stepped from 1 to 0, dc stable within 10% 1 input impedance 50 w mode, f rf = 2mhz 50 w 100 w mode, f rf = 2mhz 100 200 w mode, f rf = 2mhz 200 500 w mode, f rf = 2mhz 500 noise figure (high lna gain) r s = r in = 50 w , v gc+ - v gc- = +3v not including t/r switch 5.4 db with t/r switch 6.5 r s = r in = 100 w , v gc+ - v gc- = +3v not including t/r switch 3.9 with t/r switch 5.0 r s = r in = 200 w , v gc+ - v gc- = +3v not including t/r switch 2.8 with t/r switch 3.7 r s = r in = 500 w , v gc+ - v gc- = +3v not including t/r switch 2.1 with t/r switch 3.5 noise figure (low lna gain) r s = r in = 200 w , v gc+ - v gc- = +3v not including t/r switch 4.4 db with t/r switch 5.2 8-channel correlated noise power no input signal, ratio of 8-channel noise power to single-channel noise power 9.0 dbfs 5mhz signal applied to all 8 channels, v gc+ - v gc- = 0v, f rf = 5mhz at -3dbfs, ratio of 8-channel noise power to single-channel noise power 8.5 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 18 ac electrical characteristicsvga mode (cwd beamformer off) downloaded from: http:///
(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0c to +70c, v gnd = 0v, shdn = 0, cwd = 0, loon = 0, tmode1 = 0, tmode0 = 1, tcc1 = tcc0 = 0, thp = 1, tsync = 0, ten = 0, tinp_ = tinn_ = 1, no tclk_, f rf = 5mhz, 50mv p-p , adc f clk = 50msps, digital hpf set to 60/64, two poles, 15/16 digital gain, v gc+ - v gc- = -3v (mini - mum gain), high lna gain, connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_. typical values are at v tvdd = 3.3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25c, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units lna gain (low lna gain) 12.5 db lna gain (high lna gain) 18.5 db maximum gain (high lna gain) v gc+ - v gc- = +3v (max gain), t/r switch input to adc input 44.3 db minimum gain (high lna gain) v gc+ - v gc- = -3v (min gain), t/r switch input to adc input 4.9 db maximum gain (low lna gain) v gc+ - v gc- = +3v (max gain), t/r switch input to adc input 39.4 db minimum gain (low lna gain) v gc+ - v gc- = = -3v (min gain), t/r switch input to adc input 0.03 db gain range 39 db aa filter 3db corner frequency 9mhz setting 9 mhz 10mhz setting 10 15mhz setting 15 18mhz setting 18 aa filter 3db corner frequency accuracy 10 % digital highpass filter 3db corner frequency 2 poles, coeficients r1 = r2 = 63/64, f clk = 50msps 0.185 mhz 2 poles, coeficients r1 = r2 = 54/64, f clk = 50msps 1.736 clamp level clamp on (v p-p on aaf output/adc input, digital hpf bypassed) 92 %fs absolute gain matching t a = +25c, v gc+ - v gc- = -3v to +3v (note 10) -1.6 0.5 +1.6 db input gain compression lna = high gain, v gc+ - v gc- = -3v (vga = min gain), gain ratio with 330mv p-p /50mv p-p input tones 0.5 db lna = low gain, v gc+ - v gc- = -3v (vga = min gain), gain ratio with 600mv p-p /50mv p-p input tones 0.7 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 19 ac electrical characteristicsvga mode (cwd beamformer off) (continued) downloaded from: http:///
(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0c to +70c, v gnd = 0v, shdn = 0, cwd = 0, loon = 0, tmode1 = 0, tmode0 = 1, tcc1 = tcc0 = 0, thp = 1, tsync = 0, ten = 0, tinp_ = tinn_ = 1, no tclk_, f rf = 5mhz, 50mv p-p , adc f clk = 50msps, digital hpf set to 60/64, two poles, 15/16 digital gain, v gc+ - v gc- = -3v (mini - mum gain), high lna gain, connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_. typical values are at v tvdd = 3.3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25c, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units vga gain response time gain step up (v in = 5mv p-p , v gc+ - v gc- changed from -3v to +3v, settling time is measured within 1db inal value) 0.8 s gain step down (v in = 5mv p-p , v gc+ - v gc- changed from +3v to -3v, settling time is measured within 1db inal value) 1.8 vga output offset under pulsed overload over drive is 10ma in clamping diodes, v gc+ - v gc- = 1.0v (gain = 30db), 16 pulses at 5mhz, repetition rate 20khz; offset is measured at output when rf duty cycle is off < 3.3 %fs signal-to-noise over adc nyquist band (25mhz) v out_ = -1dbfs, v in = 200mv p-p , f rf = 5mhz at -1dbfs, anti-alias ilter = 9mhz, 50msps sample rate 67 dbfs signal-to-noise over 2mhz bandwidth v gc+ - v gc- = -1.0v (gain = 16db), v out_ = -1dbfs, v in = 200mv p-p , f rf = 5mhz at -1dbfs, anti-alias ilter = 9mhz, 50msps sample rate 76 dbfs near-carrier signal-to-noise ratio v gc+ - v gc- = 0v (gain = 22db), f rf = 5.3mhz at -1dbfs, measured at 1khz from f rf , 50msps sample rate -137 dbfs/hz second harmonic (hd2) v in = 50mv p-p , f rf = 2mhz, adc out = -3dbfs -67 dbc v in = 50mv p-p , f rf = 5mhz, adc out = -3dbfs -63 im3 distortion v in = 50mv p-p , f rf1 = 5mhz, f rf2 = 5.01mhz adc out = -3dbfs (note 11) -49 dbc nap mode power-up response time v gc+ - v gc- = 0.6v (gain = 28db), f rf = 5mhz, adc out = -3dbfs, settled with in 1db from transition on shdn pin (includes adc) 2 s nap mode power-down response time to reach dc current target 10%, on v cc5 , v cc3 , avdd, ovdd from transition on shdn pin 4 s MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 20 ac electrical characteristicsvga mode (cwd beamformer off) (continued) downloaded from: http:///
(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0c to +70c, v gnd = 0v, shdn = 0, cwd = 0, loon = 0, tmode1 = 0, tmode0 = 1, tcc1 = tcc0 = 0, thp = 1, tsync = 0, ten = 0, tinp_ = tinn_ = 1, no tclk_, f rf = 5mhz, 50mv p-p , adc f clk = 50msps, digital hpf set to 60/64, two poles, 15/16 digital gain, v gc+ - v gc- = -3v (mini - mum gain), high lna gain, connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_. typical values are at v tvdd = 3.3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25c, unless otherwise noted.) (note 3) (v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0c to +70c, v gnd = 0v, shdn = 0, cwd = 1, loon = 1, tmode1 = 0, tmode0 = 1, tcc1 = tcc0 = 0, thp = 1, tsync = 0, ten = 0, tinp_ = tinn_ = 1, no tclk_, r in = 200, ci+, ci-, cq+, cq- pulled up to +11v via four separate 0.1% 120 resistors. no rf signals a pplied, connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_. typical values are at v tvdd = 3.3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25c, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units sleep mode power-up response time v gc+ - v gc- = 0.6v (gain = 28db), f rf = 5mhz, v out_ = -1dbfs, settled within 1db from transition on shdn 2 ms sleep mode power-down response time v gc+ - v gc- = 0.6v (gain = 28db), f rf = 5mhz, dc power reaches 1mw/channel, from transition on shdn (includes adc) 4 ms adjacent-channel crosstalk v out_ = -3dbfs, f rf = 5mhz, v gc+ - v gc- = 0.6v (gain = 28db) -59 dbc alternate-channel crosstalk v out_ = -3dbfs, f rf = 5mhz, v gc+ - v gc- = 0.6v (gain = 28db) -75 dbc phase matching between channels v gc+ - v gc- = 0.6v (gain = 28db), f rf = 5mhz, v out_ = -3dbfs 1.2 degrees parameter symbol conditions min typ max units mixer lvds lo input common- mode voltage v_lvds_cm pins lo+ and lo- 1.25 0.2 v lvds lo differential input voltage v_lvds_dm common-mode input voltage = 1.25v (note 12) 200 700 mv p-p lvds lo input common-mode current i_lvds_cm input bias current, common- mode input voltage = 1.25v (note 12) 160 a lvds lo differential input resistance r_lvds_dm (note 13) 8 k w full-power mode 5v supply current per channel i_c_5v_f total i divided by 8 31.6 41 ma 3.3v supply current per channel i_c_3_3v_f total i divided by 8 1.8 3 ma MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 21 ac electrical characteristicsvga mode (cwd beamformer off) (continued) dc electrical characteristicscwd mode (vga, aaf, and adc off) downloaded from: http:///
(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0c to +70c, v gnd = 0v, shdn = 0, cwd = 1, loon = 1, tmode1 = 0, tmode0 = 1, tcc1 = tcc0 = 0, thp = 1, tsync = 0, ten = 0, tinp_ = tinn_ = 1, no tclk_, r in = 200, ci+, ci-, cq+, cq- pulled up to +11v via four separate 0.1% 120 resistors. no rf signals a pplied, connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_. typical values are at v tvdd = 3.3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25c, unless otherwise noted.) (note 3) (v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, va vdd = v ovdd = 1.7v to 1.9v, t a = 0c to +70c, v gnd = 0v, cwd = 1, shdn = 0, loon = 1, tmode1 = 0, tmode0 = 1, tcc1 = tcc0 = 0, thp = 1, tsync = 0, ten = 0, tinp_ = tinn_ = 1, no tclk_, rin = 200, f rf = 5mhz, high lna gain, ci+, ci-, cq+, cq- pulled up to +11v via four separate 0.1% 120 resistors. connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_. the rise/fall time of the lvds clock driving lo+/lo- is required to be 0.5ns, reference noise less than 10nv/ hz from 1khz to 20mhz (note 15). typical values are at v tvdd = 3.3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, t a = +25c, unless otherwise specified.) (note 3) parameter symbol conditions min typ max units 1.8v supply current per channel i_c_1_8v_f total i divided by 8, avdd + ovdd 6.3 ma 11v supply current per channel i_c_11v_f total i divided by 8 11.7 16.2 ma external reference current total current into v ref pin 70 m a on-chip power dissipation (all 8 channels) pdis_fp_tot_f (note 14) 2.1 w on-chip power dissipation per channel pdis_fp_f (note 14) 261 mw low-power mode 5v supply current per channel i_c_5v_l total i divided by 8 27 35 ma 3.3v supply current per channel i_c_3_3v_l total i divided by 8 1.8 3 ma 1.8v supply current per channel i_c_1_8v_l total i divided by 8, avdd + ovdd 6.3 a 11v supply current per channel i_c_11v_l total i divided by 8 7 ma external reference current i ref total current into the v ref pin 70 a on-chip power dissipation (all 8 channels) pdis_fp_tot_l (note 14) 1.7 w on-chip power dissipation per channel pdis_fp_l (note 14) 214 mw parameter symbol conditions min typ max units cw dopper mixermixer rf frequency range 0.9 7.6 mhz lo frequency range 8.0 60 mhz mixer output frequency range dc 100 khz MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 22 dc electrical characteristicscwd mode (vga, aaf, and adc off) (continued) ac electrical characteristicscwd mode (vga, aaf, and adc off) downloaded from: http:///
(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, va vdd = v ovdd = 1.7v to 1.9v, t a = 0c to +70c, v gnd = 0v, cwd = 1, shdn = 0, loon = 1, tmode1 = 0, tmode0 = 1, tcc1 = tcc0 = 0, thp = 1, tsync = 0, ten = 0, tinp_ = tinn_ = 1, no tclk_, rin = 200, f rf = 5mhz, high lna gain, ci+, ci-, cq+, cq- pulled up to +11v via four separate 0.1% 120 resistors. connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_. the rise/fall time of the lvds clock driving lo+/lo- is required to be 0.5ns, reference noise less than 10nv/ hz from 1khz to 20mhz (note 15). typical values are at v tvdd = 3.3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, t a = +25c, unless otherwise specified.) (note 3) parameter symbol conditions min typ max units full-power modenoise figure no carrier not including t/r switch 4.5 db with t/r switch 4.7 snr at 100mv p-p input 100mv p-p on input, f rf = f lo /8 = 1.25mhz, measured at 1khz offset -144 dbc/hz snr at 200mv p-p input 200mv p-p on input, f rf = f lo /8 = 1.25mhz, measured at 1khz offset -149 dbc/hz im3 distortion v in = 100mv p-p , f rf1 = 5mhz, f rf2 = 5.01mhz, f lo = 8 x 5mhz (note 11) -45 dbc mixer output-voltage compliance valid voltage range (ac + dc) on summed mixer output pins (note 16) 4.5 12 v channel-to-channel phase matching measured under zero beat conditions. v in = 100mv p-p , f rf = 5mhz, f lo /8 = 5mhz -1 0.5 +1 degrees channel-to-channel gain matching measured under zero beat conditions v in = 100mv p-p , f rf = 5mhz, f lo /8 = 5mhz -1 0.5 +1 db transconductance f lo /8 = 1.25mhz (note 17) 20 23 27.5 ms low-power mode noise figure no carrier not including t/r switch 4.4 db with t/r switch 4.6 snr at 100mv p-p input 100mv p-p on input, f rf = f lo /8 = 1.25mhz, measured at 1khz offset -144 dbc/hz snr at 200mv p-p input 200mv p-p on input, f rf = f lo /8 = 1.25mhz, measured at 1khz offset -148 dbc/hz im3 distortion v in = 100mv p-p , f rf1 = 5mhz, f rf2 = 5.01mhz, f lo = 8 x 5mhz (note 11) -44 dbc mixer output-voltage compliance valid voltage range (ac+dc) on summed mixer output pins (note 16) 4.5 12 v transconductance f lo /8 = 1.25mhz (note 17) 19 21 26.5 ms MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 23 ac electrical characteristicscwd mode (vga, aaf, and adc off) (continued) downloaded from: http:///
(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0c to +70c, v gnd = 0v, shdn = 0, cwd = 0, loon = 0, tmode1 = 0, tmode0 = 1, tcc1 = tcc0 = 0, thp = 1, tsync = 0, ten = 0, tinp_ = tinn_ = 1, no tclk_, f rf = 5mhz, 50mv p-p , connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_. typical values are at v tvdd = 3.3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25c, unless otherwise noted.) (note 3, note 18) parameter symbol conditions min typ max units clock inputs (clkin+, clkin-) differential mode differential clock input voltage 0.4 to 2.0 v p-p common-mode voltage v clkcm self-biased 1.2 v dc-coupled clock signal 1.0 to 1.4 input resistance r clk differential, default setting 10 k w differential, programmable internal termination selected 0.1 common mode to gnd 9 input capacitance c clk capacitance to gnd, each input 3 pf clock inputs (clkin+, clkin-) single-ended mode (clkin- < 0.1v)single-ended mode-selection threshold (clkin-) 0.1 v single-ended clock input high threshold (clkin+) 1.5 v single-ended input clock low threshold (clkin+) 0.3 v input leakage (clkin+) v ih = 1.8v +5 a v il = 0v -5 a input leakage (clkin-) v il = 0v -150 -50 a input capacitance (clkin+) 3 pf digital inputs (cwd, loon, shdn, sclk, sdio, cs) high-level input threshold v ih 1.5 v low-level input threshold v il 0.3 v logic-input leakage i ih v ih = 1.8v +5 a i il v il = 0v -5 logic-input capacitance c din 3 pf digital outputs (sdio) high-level output voltage v oh i source = -200a v ovdd C 0.2 v low-level output voltage v ol i sink = 200a 0.2 v lvds digital outputs (out_, clkout, frame) (i = 3.5ma, v cm = 1.2v) differential output voltage | v od | r load = 100 w 225 300 490 mv output offset voltage v os 1.125 1.200 1.375 v MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 24 electrical characteristicsafe clock and timing downloaded from: http:///
(v ref = 2.5v, v cc3 = 3.13v to 3.47v, v cc5 = 4.5v to 5.25v, v avdd = v ovdd = 1.7v to 1.9v, t a = 0c to +70c, v gnd = 0v, shdn = 0, cwd = 0, loon = 0, tmode1 = 0, tmode0 = 1, tcc1 = tcc0 = 0, thp = 1, tsync = 0, ten = 0, tinp_ = tinn_ = 1, no tclk_, f rf = 5mhz, 50mv p-p , connect c = 1f between tvpp_ to tvgp_ and tvnn_ to tvgn_. typical values are at v tvdd = 3.3v, v tvcc = 5v, v tvee = -5v, v tvnn_ = -100v, v tvpp_ = 100v, v cc3 = 3.3v, v cc5 = 4.75v, v avdd = v ovdd = 1.8v, v gc+ - v gc- = 0v, t a = +25c, unless otherwise noted.) (note 3, note 18) note 3: minimum and maximum limits at t a = +25c and +70c are guaranteed by design, characterization, and/or production test. note 4: maximum operating current from v tvgn_ and v tvgp_ external power sources can vary depending on application require - ments. the suggested typical values assume 8 channels running in continuous transmission (cwd) at 5mhz with tcc0 = tcc1 = high. note 5: cw doppler: continuous wave, f = 5mhz, v dd = +3v, v cc = -v ee = +5v, v pp_ = -v nn_ = +5v. note 6: b mode: f = 5mhz, p rf = 5khz, 1 period, v dd = +3v, v cc = -v ee = +5v, v pp_ = -v nn_ = +100v. note 7: this response time does not include the cw output highpass filter. when switching to vga mode, the cw outputs stop drawing current and the output voltage goes to the rail. if a highpass filter is used, the recovery time may be excessive and a switching network is recommended. note 8: t/r switch turn-off time is the time required to switch off the bias current of the t/r switch. the off-isolation is not guaran - teed. note 9: noise performance of the device is dependent on the noise contribution from v ref . use a low-noise supply for v ref . note 10: absolute gain matching is defined as the gain difference between any single channel and the average of numerous chan - nels across multiple devices. this specification is valid for all vga gain settings for devices sharing the same control volt - ages v gc+ , v gc-. note 11: see in the ultrasound-specific imd3 specification section. parameter symbol conditions min typ max units serial-port interface timing sclk period t sclk 50 ns sclk-to- cs setup time t css 10 ns sclk-to- cs hold time t csh 10 ns sdio-to-sclk setup time t sds serial-data write 10 ns sdio-to-sclk hold time t sdh serial-data write 0 ns sclk-to-sdio output data delay t sdd serial-data read 10 ns lvds digital output timing characteristics data valid to clkout_ rise/fall t od (t sample /24) - 0.10 (t sample /24) + 0.05 (t sample /24) + 0.20 ns clkout_ output-width high t ch t sample /12 ns clkout_ output-width low t cl t sample /12 ns frame_ rise to clkout_ rise t df (t sample /24) - 0.10 (t sample /24) + 0.05 (t sample /24) + 0.20 ns sample clkin_ rise to frame_ rise t sf (t sample /2) + 1.6 (t sample /24) + 2.3 (t sample /24) + 3.3 ns cwd lo timing loon setup time t su setup time from loon high to lvds lo clock low-to-high transition (figure 1) 5 ns MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 25 electrical characteristicsafe clock and timing (continued) downloaded from: http:///
note 12: the lvds cwd lo clocks are dc-coupled. see the cwd beamformer programming and clocking section for details of lo startup synchronization. note 13: an external 100? resistor terminates the lvds differential signal path (lo+, lo-). note 14: total on-chip power dissipation is calculated as p diss = v cc5 x i cc5 + v cc3 x i cc3 + v avdd x i avdd + v ovdd x i ovdd + v ref x i ref + [11v - (i11v/4) x 120] x i11v + v tvcc x i tvcc + v tvee x i tvee + v tvdd x i tvdd . additional power is dissipated through the off-chip, 120? load resistors. note 15: the reference input noise is given for 8 channels, knowing that the reference-noise contributions are correlated in all 8 channels. if more channels are used, the reference noise must be reduced to get the best noise performance. note 16: mixer output-voltage compliance is the range of acceptable voltages allowed on the cw mixer outputs. note 17: transconductance is defined as the differential output current at baseband for each individual (i or q) mixer output, divided by the single-ended, rf input voltage directly on a single, t/r switch input pin (trj). this can be calculated as g mi = (i ci+ - i ci- )/v trj and gmq = (i cq+ - i cq- )/vtrj; or equivalently as gmi = (v ci+ - v ci- )/(r l x vtrj) and g mq = (i cq+ - i cq- )/(r l x vtrj) (where j = 1, 2,8 is a specific channel number, trj is a single t/r switch input pin, and r l is the load resistance on each, individual mixer output pin). note 18: all currents are global. in particular, i nn_ = i tvnna + i tvnnb , i pp_ = i tvppa + i tvppb . figure 1. cwd loon lo turn-on/turn-off setup time figure 2. hv burst test (three levels) t su lo+ lvds lo lo- loon v tvppa = v tvppb 200ns v tvnna = v tvnnb 200s MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 26 timing diagrams downloaded from: http:///
figure 3. propagation delay timing figure 4. output rise/fall timing tr_ tinp_ tinn_ v tvpp_ gndv tvnn_ v tvdd gndv tvdd gnd 10% 50% 50% 50% 50% t ph0 t plh t phl t pl0 10% 10% 10% tr_ v tvpp_ gndv tvnn_ t rop t rnp t fpn t fpo 80% 80% 20% 80% 80% 20% 80% 80% 20% 80% 20% 80% t fon t rno MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 27 timing diagrams (continued) downloaded from: http:///
figure 5. t/r switch turn-on/off time MAX2082 tinp_ v tvdd v rif r l = 1k i r l = 1k i tinn_ 0v ~0v v tvnn_ tinp_ inb_ tr_ v tvdd v rif /(2 x r l + r on ) x (r on + r l ) v rif /(2 x r l + r on ) x r l inb_tr_ t ontrsw t offtrsw MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 28 timing diagrams (continued) downloaded from: http:///
figure 6. bandwidth v tvdd v tvdd v tvppa / v tvppb v tvnna / v tvnnb gndgnd gnd tinp_ tr_ tinn_ 90% v tvppa / v tvppb 90% v tvnna / v tvnnb timing diagrams (continued) MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 29 downloaded from: http:///
figure 7. jitter timing v tvdd v tvdd v tvppa /v tvppb v tvnna /v tvnnb gndgnd tinp_ tinn_ tr_ t dr t jr = d t dr 50% 50% 50% 50% t df t jf = d t df MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 30 timing diagrams (continued) downloaded from: http:///
0 2 4 6 8 10 12 2.5 3 3.5 4 4.5 5 5.5 i cc , |i ee | supply current (ma) v cc , |v ee | supply voltage (v) i cc , |i ee | supply current vs. v cc , |v ee | supply voltage toc01 all channels on 0 5 10 15 20 25 30 35 40 45 50 -3 -2 -1 0 1 2 3 gain (db) control voltage (v) gain vs. differential analog control voltage toc02 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 30 40 50 60 70 0 5 10 15 20 25 input impedance, imaginary part ( ) input impedance, real part ( ) frequency (mhz) complex input impedance vs. frequency (18.5db lna gain, 50 ) toc03 real imaginary -100 -90 -80 -70 -60 -50 -40 -30 -20 50 60 70 80 90 100 110 0 5 10 15 20 25 input impedance, imaginary part ( ) input impedance, real part ( ) frequency (mhz) complex input impedance vs. frequency (18.5db lna gain, 100 ) toc04 real imaginary -110 -100 -90 -80 -70 -60 -50 -40 50 70 90 110 130 150 170 190 210 0 5 10 15 20 25 input impedance, imaginary part ( ) input impedance, real part ( ) frequency (mhz) complex input impedance vs. frequency (18.5db lna gain, 200 ) toc05 real imaginary -400 -350 -300 -250 -200 -150 -100 -50 0 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 0 5 10 15 20 25 input impedance, imaginary part ( ) input impedance, real part ( ) frequency (mhz) complex input impedance vs. frequency (18.5db lna gain, 500 ) toc06 real imaginary 0 5 10 15 20 25 30 35 40 45 50 18.7 18.8 18.9 19.0 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 occurrence (%) gain (db) gain distribution v gc+ - v gc - = - 0.35v toc07 0 50 100 150 200 250 0 10 20 30 40 50 total output noise (nv/ hz ) gain (db) total output spot noise vs. gain toc08 aaf = 9mhz 5mhz center frequency 1mhz spot bandwidth MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer maxim integrated 31 www.maximintegrated.com (t a = +25c, unless otherwise noted.) typical operating characteristics downloaded from: http:///
(t a = +25c, unless otherwise noted.) -70 -69 -68 -67 -66 -65 -64 -63 -62 -61 -60 -59 -58 -57 -56 -55 0 10 20 30 40 50 total output noise (dbfs) gain (db) total output noise vs. gain toc09 aaf = 9mhz aaf = 10mhz aaf = 15mhz aaf = 18mhz 0 5 10 15 20 25 30 0 10 20 30 40 50 total input noise (nv/ hz ) gain (db) total input spot noise vs. gain toc10 aaf = 9mhz 5mhz center frequency 1mhz spot bandwidth -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 5 10 15 20 25 30 35 40 45 hd2 (dbc) gain (db) second harmonic distortion vs. gain 9mhz aaf setting toc11 v in = 100mv p-p , gain 21db v out = - 3.5dbfs, gain > 21db f rf = 2mhz f rf = 5mhz -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 5 10 15 20 25 30 35 40 45 hd2 (dbc) gain (db) second harmonic distortion vs. gain 10mhz aaf setting toc12 v in = 100mv p-p , gain 21db v out = - 3.5dbfs, gain > 21db f rf = 2mhz f rf = 5mhz -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 5 10 15 20 25 30 35 40 45 hd2 (dbc) gain (db) second harmonic distortion vs. gain 15mhz aaf setting toc13 v in = 100mv p-p , gain 21db v out = - 3.5dbfs, gain > 21db f rf = 2mhz f rf = 5mhz f rf = 10mhz -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 5 10 15 20 25 30 35 40 45 hd2 (dbc) gain (db) second harmonic distortion vs. gain 18mhz aaf setting toc14 v in = 100mv p-p , gain 21db v out = - 3.5dbfs, gain > 21db f rf = 2mhz f rf = 5mhz f rf = 10mhz -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 5 10 15 20 25 30 35 40 45 hd3 (dbc) gain (db) third harmonic distortion vs. gain 9mhz aaf setting toc15 v in = 100mv p-p , gain 21db v out = - 3.5dbfs, gain > 21db f rf = 2mhz f rf = 5mhz -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 5 10 15 20 25 30 35 40 45 hd3 (dbc) gain (db) third harmonic distortion vs. gain 10mhz aaf setting toc16 v in = 100mv p-p , gain 21db v out = - 3.5dbfs, gain > 21db f rf = 2mhz f rf = 5mhz MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer maxim integrated 32 www.maximintegrated.com typical operating characteristics (continued) downloaded from: http:///
(t a = +25c, unless otherwise noted.) -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 5 10 15 20 25 30 35 40 45 hd3 (dbc) gain (db) third harmonic distortion vs. gain 15 mhz aaf setting toc17 v in = 100mv p-p , gain 21db v out = - 3.5dbfs, gain > 21db f rf = 2mhz f rf = 5mhz f rf = 10mhz -110 -100 -90 -80 -70 -60 -50 -40 5 10 15 20 25 30 35 40 45 hd3 (dbc) gain (db) third harmonic distortion vs. gain 18mhz aaf setting toc18 v in = 100mv p-p , gain 21db v out = - 3.5dbfs, gain > 21db f rf = 2mhz f rf = 5 mhz f rf = 10mhz -80 -70 -60 -50 0 2 4 6 8 10 12 hd2 and hd3 (dbc) frequency (mhz) second and third harmonic distortion vs. frequency toc19 v out = - 3.5dbfs gain 26db hd2 hd3 -70 -65 -60 -55 -50 -45 -40 5 10 15 20 25 30 35 40 45 im3 (dbc from smaller signal) gain (db) im3 distortion vs. gain toc20 f 1 = 5mhz, v in at f 1 = 50mv p-p (gain 27db) v out at f 1 = - 3.5 dbfs (gain > 27db) f 2 = 5.01mhz, v in at f 2 = - 25dbc aaf = 15mhz -110 -100 -90 -80 -70 -60 -50 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 hd2 and hd3 (dbc) adc output (dbfs) second and third harmonic distortion vs. adc output toc21 gain 26db hd2 hd3 -70 -65 -60 -55 -50 -45 0 1 2 3 4 5 6 7 8 9 10 11 12 im3 (dbc from smaller signal) frequency (mhz) im3 distortion vs. frequency toc22 v in = 50mv p-p gain 21db -75 -70 -65 -60 -55 5 10 15 20 25 30 35 40 45 crosstalk (dbc) gain (db) adjacent channel - to - channel crosstalk vs. gain 2mhz input toc23 v in = 200mv p-p , gain 16db v out = - 3.5dbfs, gain > 16db adjacent channel 1 adjacent channel 2 -80 -75 -70 -65 -60 5 10 15 20 25 30 35 40 45 crosstalk (dbc) gain (db) alternate channel - to - channel crosstalk vs. gain 2mhz input toc24 v in = 200mv p-p , gain 16db; v out = - 3.5 dbfs, gain > 16db, alternate channel 1 alternate channel 2 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer maxim integrated 33 www.maximintegrated.com typical operating characteristics (continued) downloaded from: http:///
(t a = +25c, unless otherwise noted.) -70 -65 -60 -55 -50 5 10 15 20 25 30 35 40 45 crosstalk (dbc) gain (db) alternate channel - to - channel crosstalk vs. gain 10mhz input toc28 v in = 200mv p-p , gain 16db v out = - 3.5dbfs, gain > 16db alternate channel 1 alternate channel 2 -100 -90 -80 -70 -60 -50 -40 -30 0.1 1 10 100 crosstalk (dbc) frequency (mhz) alternate channel - to - channel crosstalk vs. frequency alternate channel 1 toc30 v in = 100mv p-p alternate channel 2 -100 -90 -80 -70 -60 -50 -40 -30 0.1 1 10 100 crosstalk (dbc) frequency (mhz) adjacent channel - to - channel crosstalk vs. frequency adjacent channel 1 toc29 v in = 100mv p-p adjacent channel 2 -10 -5 0 5 10 15 20 25 0 5 10 15 20 25 gain (db) frequency (mhz) large - signal bandwidth vs. frequency (gain = 20db) toc31 v out - max = - 3.5dbfs, gain = 20db 18mhz aaf 15mhz aaf 10mhz aaf 9mhz aaf -70 -65 -60 -55 -50 5 10 15 20 25 30 35 40 45 crosstalk (dbc) gain (db) adjacent channel - to - channel crosstalk vs. gain 5mhz input toc25 v in = 200mv p-p , gain 16db v out = - 3.5dbfs, gain > 16db adjacent channel 1 adjacent channel 2 -75 -70 -65 -60 -55 5 10 15 20 25 30 35 40 45 crosstalk (dbc) gain (db) alternate channel - to - channel crosstalk vs. gain 5mhz input toc26 v in = 200mv p-p , gain 16db v out = - 3.5dbfs, gain > 16db alternate channel 1 alternate channel 2 -65 -60 -55 -50 -45 5 10 15 20 25 30 35 40 45 crosstalk (dbc) gain (db) adjacent channel - to - channel crosstalk vs. gain 10mhz input toc27 v in = 200mv p-p , gain 16db v out = - 3.5dbfs, gain > 1db adjacent channel 1 adjacent channel 2 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer maxim integrated 34 www.maximintegrated.com typical operating characteristics (continued) downloaded from: http:///
(t a = +25c, unless otherwise noted.) -10 -5 0 5 10 15 20 25 0.1 1 10 100 gain (db) frequency (mhz) large - signal bandwidth vs. frequency (gain = 20db) toc32 v out - max = - 3.5dbfs, gain = 20db 18mhz aaf 15mhz aaf 10mhz aaf 9mhz aaf 0 500 1000 1500 2000 2500 3000 3500 4000 0 1 2 3 4 5 6 code values time (s) lna overload recovery (digital hpf disabled) toc33 tx pulse 5mhz 6v p-p from open circuit 16 cycles, 50s period gain = 30db rf input = 6.4mv p-p at 5mhz cw 0 500 1000 1500 2000 2500 3000 3500 4000 0 1 2 3 4 5 6 code values time (s) lna overload recovery (digital hpf enabled) toc34 tx pulse 5mhz 6v p-p from open circuit 16 cycles, 50s period gain = 30db rf input = 6.4mv p-p at 5mhz cw 0 500 1000 1500 2000 2500 3000 3500 4000 0 1 2 3 4 5 code values time (s) vga overload recovery (digital hpf disabled) toc35 70 cycles, 66s period gain = max db rf input = - 46dbm at 5mhz cw tx pulse 5mhz, 6v p- p open ckt -160 -140 -120 -100 -80 -60 -40 -20 0 20 0 5 10 15 20 25 amplitude (dbfs) frequency(mhz) fft plot 8192 points toc37 v in = 100mv p-p gain 20db v out = - 3.5dbfs (unwindowed) aaf = 9mhz 0 500 1000 1500 2000 2500 3000 3500 4000 0 1 2 3 4 5 code values time (s) vga overload recovery (digital hpf enabled) toc36 70 cycles, 66s period gain = max db rf input = - 46dbm at 5mhz cw tx pulse 5mhz, 6v p-p open ckt 56 58 60 62 64 66 68 0 10 20 30 40 50 snr (dbfs) gain (db) snr vs. gain toc38 v in = 200mv p-p , gain 16db; v out = - 1dbfs, gain > 16db, aaf = 9mhz MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer maxim integrated 35 www.maximintegrated.com typical operating characteristics (continued) downloaded from: http:///
(t a = +25c, unless otherwise noted.) 65 65.5 66 66.5 67 67.5 68 68.5 69 69.5 70 -10 -8 -6 -4 -2 0 snr (dbfs) adc output (dbfs) snr vs. adc output toc39 v in = 200mv p-p , max at 5.3mhz, gain = 20db, aaf = 9mhz 0 500 1000 1500 2000 2500 3000 3500 4000 -2 -1 0 1 2 3 4 5 6 7 8 code values time (s) vga gain control response time (up) toc40 gc transition at t = 0 min gain to max gain 0 500 1000 1500 2000 2500 3000 3500 4000 -2 -1 0 1 2 3 4 5 6 7 8 code values time (s) vga gain control response time (down) toc41 gc transition at t = 0 max gain to min gain -25 -20 -15 -10 -5 0 5 0.1 1 normalized gain (db) frequency (mhz) digital highpass filter normalized magnitude responses vs. frequency, first section (hpf1) toc42 r1 = bypass r1 = 63/64 r1 = 54/64 -25 -20 -15 -10 -5 0 5 0.1 1 normalized gain (db) frequency (mhz) digital highpass filter normalized magnitude responses vs. frequency, both sections (hpf1 + hpf2) toc44 r1 = r2 = bypass r1 = r2 = 63/64 r1 = r2 = 54/64 -15 -10 -5 0 5 0.1 1 attenuation (db) frequency (mhz) input network attenuation due to ac - coupling vs. frequency toc43 -25 -20 -15 -10 -5 0 5 0.1 1 normalized gain (db) frequency (mhz) digital highpass filter normalized magnitude responses vs. frequency, both sections (hpf1 + hpf2) toc45 r1 = r2 = bypass r1 = r2 = 63/64 r1 = r2 = 54/64 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer maxim integrated 36 www.maximintegrated.com typical operating characteristics (continued) downloaded from: http:///
gnd tinn1 gnd gnd tr6 tinn2 tinp2 gnd tinp3 tinp4 gnd tr7 gnd tinp1 tinn4 gnd tr8 tinn3 gnd tvdd tr4 gndgnd tinp8 tinp6 tr5 tvnnb gnd tinp7 tsync tinp5 tmode1 tmode0 gnd gnd gnd tvdd gnd tclk+ tcc1 tcc0 gnd tvgpb tvppb tvee 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 9 10 23mm x 10mm (0.8mm pitch) 28 x 12 ctbga 11 12 tvppa tvnna tvgpa tvee tr1 tvnna tvppa tvcc gnd gnd gnd gnd gnd gnd gnd gnd gnd inb1 gnd gnd inb2 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd v cc5 v cc3 v cc5 gnd gnd gnd gnd gnd gnd gnd gnd inb3 gnd gnd gnd 13 14 15 16 17 18 12 13 14 15 16 17 18 1919 tvgna tr2 tvnna gnd tvppa tvnna tr3 gnd tvppa gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd inb4 gnd gnd gnd tvnna gnd tvppa gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd ag gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd ag gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd inb5 gnd gnd gnd tvnnb gnd tvppb gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd inb6 gnd gnd gnd tvnnb gnd tvppb gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd inb7 gnd gnd gnd tvnnb gnd tvppb tinn6 tinn7 tvcc tinn5 ten tinn8 thp tclk- gnd gnd gnd inb8 gnd gnd v cc5 tvnnb tvgnb tvppb gnd a b cd e f g h j k l m a b cd e f g h j k l m top view ci+ gnd ci- cq- gnd cq+ v cc5 v cc3 lo+ lo- gc+ gnd avdd avdd loon gnd 20 21 22 23 avdd gnd i.c. refio ognd cwd ognd out2- n.c. out1+ out1- shdn out2+ ovdd csb gnd sclk clkin- gnd ovdd gnd gnd gnd gnd gnd ognd out3- out3+ gnd 24 25 26 27 28 20 21 22 23 24 25 26 27 28 gnd gnd gnd gnd gnd ognd out4- out4+ gnd gnd gnd gnd gnd gnd ovdd clkout- clkout+ gnd gnd gnd gnd gnd gnd ovdd frame- frame+ gnd gnd gnd gnd gnd gnd ognd out5- out5+ gnd gnd gnd gnd gnd gnd ognd out6- out6+ gnd gnd gnd gnd gnd gnd ognd out7- out7+ gnd gc- ref v cc3 avdd clkin+ sdio out8- out8+ gnd MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 37 bump coniguration downloaded from: http:///
bump name function a1, a13Ca18, a27, b10, b13-b15, b17, b18, c4-c15, c17-c26, d4- d15, d17-d26, e4-e15, e17-e26, f1-f17, f19-f25, g1-g17, g19-g25, h4- h15, h17-h26, j4-j15, j17-j26, k4-k15, k17-k26, l13-l15, l17, l18, l25, m1, m13-m18, m25 gnd ground a2, b2, c2, d2, e2 tvnna high-voltage negative supply input. bypass tvnna to gnd with a 0.1f capacitor as close as possible to the device. a3, b3, c3, d3, e3 tvppa high-voltage positive supply input. bypass tvppa to gnd with a 0.1f capacitor as close as possible to the device. a4 tvgpa driver voltage supply output. connect 1f capacitor to tvppa as close as possible to the device. a5, m5 tvee tvee supply voltage input. bypass tvee (both pins) to gnd with a 0.1f capacitor as close as possible to the device. a6 tinp1 digital signal positive input 1 (see table 1). a7 tinp2 digital signal positive input 2 (see table 1). a8 tinp3 digital signal positive input 3 (see table 1). a9 tinp4 digital signal positive input 4 (see table 1). a10, m10 tvdd logic supply voltage input. bypass tvdd (both pins) to gnd with a 0.1f capacitor as close as possible to the device. a11 tmode1 mode control input. control operation mode (see table 1). a12 tcc1 current control input. control current capability (see table 2). a19, l22, m22 v cc3 3.3v power-supply voltage input. bypass to gnd with a 0.1f capacitor as close as possible to the part. a20 ci+ 8-channel cw positive in-phase output. connect to 11v with a 120? external resistor. a21 cq+ 8-channel cw positive quadrature output. connect to 11v with a 120? external resistor. a22 lo+ positive cw local oscillator input. this clock is then divided in the beamformer. a23, b24, l23, m23 avdd 1.8v analog adc power-supply voltage input. bypass avdd to gnd with a 0.1f capacitor as close as possible to the device. a24 n.c. no connection. not internally connected. a25 refio i/o reference (for internal calibration). bypass refio to gnd with a 0.1f capacitor as close as possible to the device (do not drive refio). MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 38 bump description downloaded from: http:///
bump name function a26 cwd vga/cw mode select. set cwd low to enable the vgas and disable the cw mixers. set cwd high to enable the cw mixers and disable the vgas. a28, f26, g26, m28 ovdd 1.8v digital adc power-supply voltage input. bypass ovdd to gnd with a 0.1f capacitor as close as possible to the device. b1 tr1 transmit pulser output, receiver input channel 1 b4 tvgna driver voltage supply output. connect 1f capacitor to tvnna as close as possible to the device. b5, l5 tvcc tvcc supply voltage input. bypass tvcc (both pins) to gnd with a 0.1f capacitor as close as possible to the device. b6 tinn1 digital signal negative input 1 (see table 1). b7 tinn2 digital signal negative input 2 (see table 1). b8 tinn3 digital signal negative input 3 (see table 1). b9 tinn4 digital signal negative input 4 (see table 1). b11 tmode0 mode control input. control operation mode (see table 1). b12 tcc0 current control input. control current capability (see table 2). b16 inb1 low voltage t/r switch output/lna input channel 1 b19, l19, m19, m20 v cc5 4.75v power-supply voltage input. bypass to gnd with a 0.1f capacitor as close as possible to the device. b20 ci- 8-channel cw negative in-phase output. connect to 11v with a 120? external resistor. b21 cq- 8-channel cw negative quadrature output. connect to 11v with a 120 ? external resistor. b22 lo- negative cw local oscillator input. this clock is then divided in the beamformer. b23 loon lo on control input. turns lo on starting on the next rising or falling edge of lo. b25 i.c. internally connected. leave unconnected. b26 shdn power-down (nap or sleep mode programmable through serial interface) b27 out1+ channel 1 positive lvds output b28 out1- channel 1 negative lvds output c1 tr2 transmit pulser output, receiver input channel 2 c16 inb2 low voltage t/r switch output/lna input channel 2 c27 out2+ channel 2 positive lvds output c28 out2- channel 2 negative lvds output d1 tr3 transmit pulser output, receiver input channel 3 d16 inb3 low voltage t/r switch output/lna input channel 3 d27 out3+ channel 3 positive lvds output d28 out3- channel 3 negative lvds output e1 tr4 transmit pulser output, receiver input channel 4 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 39 bump description (continued) downloaded from: http:///
bump name function e16 inb4 low voltage t/r switch output/lna input channel 4 e27 out4+ channel 4 positive lvds output e28 out4- channel 4 negative lvds output f18, g18 ag analog ground for lna inputs. leave ag unconnected. f27 clkout+ positive lvds serial-clock output f28 clkout- negative lvds serial-clock output g27 frame+ positive frame-alignment lvds output g28 frame- negative frame-alignment lvds output h1 tr5 transmit pulser output, receiver input channel 5 h2, j2, k2, l2, m2 tvnnb high-voltage negative supply input. bypass tvnnb to gnd with a 0.1f capacitor as close as possible to the device. h3, j3, k3, l3, m3 tvppb high-voltage positive supply input. bypass tvppb to gnd with a 0.1f capacitor as close as possible to the device. h16 inb5 low voltage t/r switch output/lna input channel 5 h27 out5+ channel 5 positive lvds output h28 out5- channel 5 negative lvds output j1 tr6 transmit pulser output, receiver input channel 6 j16 inb6 low voltage t/r switch output/lna input channel 6 j27 out6+ channel 6 positive lvds output j28 out6- channel 6 negative lvds output k1 tr7 transmit pulser output, receiver input channel 7 k16 inb7 low voltage t/r switch output/lna input channel 7 k27 out7+ channel 7 positive lvds output k28 out7- channel 7 negative lvds output l1 tr8 transmit pulser output, receiver input channel 8 l4 tvgnb driver voltage supply output. connect 1f capacitor to tvnnb as close as possible to the device. l6 tinn5 digital signal negative input 5 (see table 1). l7 tinn6 digital signal negative input 6 (see table 1). l8 tinn7 digital signal negative input 7 (see table 1). l9 tinn8 digital signal negative input 8 (see table 1). l10 ten internal supply generator control input. drive ten high to disable the internal power supply when using an external power supply on tvgpa, tvgpb, tvgna, and tvgnb. ten has an internal 10k? pulldown resistor to gnd. l11 thp open-drain thermal-protection output. thp asserts and sinks a 3ma current to gnd when the junction temperature exceeds +150 c. MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 40 bump description (continued) downloaded from: http:///
bump name function l12 tclk- cmos control input. clock negative phase input. data inputs are clocked in at the edge of tclk+ and tclk- in differential clocked mode. clock maximum frequency is 160mhz (max). if tclk- is connected to gnd, tclk+ input is single-ended logic-level clock input. otherwise, tclk and tclk+ are self-biased differential clock inputs. l16 inb8 low voltage t/r switch output/lna input channel 8 l20 v ref voltage reference input. bypass v ref to gnd with a capacitor. l21 gc- negative gain control voltage. set v gc+ - v gc- = +3v for maximum gain. set v gc+ - v gc- = -3v for minimum gain. l24 clkin+ positive differential adc clock input l26 sdio serial-data input l27 out8+ channel 8 positive lvds output l28 out8- channel 8 negative lvds output m4 tvgpb driver voltage supply output. connect 1f capacitor to tvppb as close as possible to the device. m6 tinp5 digital signal positive input 5 (see table 1). m7 tinp6 digital signal positive input 6 (see table 1). m8 tinp7 digital signal positive input 7 (see table 1). m9 tinp8 digital signal positive input 8 (see table 1). m11 tsync cmos control input. drive tsync high to enable clocked-input mode. drive tsync low to operate in transparent mode (see the truth tables section). m12 tclk+ cmos control input. clock positive phase input. data inputs are clocked in at the rising edge of tclk in differential clocked mode or at the rising edge of tclk+ in single-ended clocked mode. clock maximum frequency is 160mhz. m21 gc+ postive gain control voltage. set v gc+ - v gc- = +3v for maximum gain. set v gc+ - v gc- = -3v for minimum gain. m24 clkin- negative differential adc clock input. connect to gnd for a single ended clock m26 sclk serial-clock input. m27 cs chip select MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 41 bump description (continued) downloaded from: http:///
frame+frame- pll 1x6x clock circuitry out1+ ovdd avdd sclk sdio csb cwd v cc3 v cc5 tclk- tclk+ tsync thp ten cq- cq+ ci- ci+ loon lo+ lo- out1- ognd refio dout shdn gnd gc- gc+ ref inc ag tmode1 tmode0 tcc1 tcc0 tvgnb tvgpb tvnnb tvppb tvgna tvgpa tvnna tvppa tvdd tvcc tvee inb1 tvpp tvnn tvpp tvnn tvpp tvnn tvpp tvnn tvpp tvnn tvpp tvnn tvpp tvnn tvpp tvnn tinp1 tinn1 tr1 clkout+ clkout- clkin+ clkin- o1- tvcctvee tvcc tvee digital hp filter adc serializer tvcctvee tvcc tvee adc digital hp filter out2+out2- serializer o2- o2+ aaf vga lna tvcctvee tvcc tvee adc digital hp filter out3+out3- serializer o3- o3+ aaf vga lna tvcctvee tvcc tvee adc digital hp filter out4+out4- serializer o4- o4+ aaf vga lna tvcctvee tvcc tvee adc digital hp filter out5+out5- serializer o5- o5+ aaf vga lna tvcctvee tvcc tvee adc digital hp filter out6+out6- serializer o6- o6+ aaf vga lna tvcctvee tvcc tvee adc digital hp filter out7+out7- serializer o7- o7+ aaf vga lna tvcctvee tvcc tvee adc digital hp filter out8+out8- serializer o8- o8+ aaf vga lna aaf vga lna o1+ inb2 tinp2 tinn2 tr2 inb3 tinp3 tinn3 tr3 inb4 tinp4 tinn4 tr4 inb5 tinp5 tinn5 tr5 inb6 tinp6 tinn6 tr6 inb7 tinp7 tinn7 tr7 inb8 tinp8 tinn8 tr8 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 42 functional diagram downloaded from: http:///
detailed description the MAX2082 is a fully integrated high-density octal ultra - sound transceiver optimized for low-cost, high-channel count, high-performance portable and cart based ultra - sound systems. the easy-to-use integrated receiver allows the user to achieve high-end 2d and doppler imag - ing capability using substantially less space and power. the integrated octal 3-level pulser, t/r switch, input coupling caps, lna, vga, aaf, adc, and digital hpf achieves an ultra-low noise figure with a low per channel power dissipation at 50msps. the transmitters are high-performance, three-level, 2a, high-voltage (hv) pulser devices capable of generating high-frequency, hv bipolar pulses (up to 105v) from low- voltage control logic inputs for driving. all eight channels have embedded overvoltage-protection diodes and inte - grated active return-to-zero clamp. these pulsers have embedded independent (floating) power supplies (fpss) and level shifters that allow signal transmission without the need for external hv capacitors. each channel is controlled by two logic inputs (tinn_/ tinp_) and the active return to zero features half the cur - rent driving of the pulser (1a typ). the pulsers can operate both in clocked and transparent mode. in clocked mode, data inputs can be synchronized with a clean differential or single-ended clock to reduce phase noise associated with fpga output signals that are detrimental for doppler analysis. in transparent mode, the synchronization feature is disabled and output reflects the data input after an 18ns delay. an adjustable maximum current (0.5a to 2a) reduces power consumption when full current capability is not required. the pulsers feature integrated grass-clipping diodes (with low parasitic capacitance) for receive (rx) and transmit (tx) isolations. a damping circuit fully discharges the puls - ers output internal node before the grass-clipping diodes. this damping circuit (typically 500? can be activated as soon as the transmit burst is over. the full receive channel has been optimized for second- harmonic imaging. dynamic range is also optimized for exceptional pulsed and color flow doppler performance under high-clutter conditions. the bipolar front-end and cmos adc have also been optimized for an exception - ally low near carrier modulation noise for excellent low velocity doppler sensitivity. the MAX2082 also includes an octal cwd beamformer for a full doppler solution. separate mixers for each chan - nel are made available for optimal cwd sensitivity. transmit pulser modes of operation operating modes for the pulsers and t/r switches are controlled by tmode[1:0] (table 1 ). shutdown mode (tmode0, tmode1 = 00) all channels are disabled, no transmission/ reception is possible. this mode has the lowest power consump - tion for the pulsers and t/r switch. shut down the afe through the serial interface to further reduce power con - sumption.octal 3 level mode (tmode0, tmode1 = 10) the pulser uses all eight independent channels. each channel can generate a three-level pulse. the high-side and low-side fet of each channel are capable of provid - ing 2.0a current, while the clamp is capable of 1a current. disable transmit mode (tmode0, tmode1 = 11) all eight high-voltage transmit channels are disabled, no pulse transmission is possible. the t/r switch can be turned on (to receive low-voltage signals) or off (for isola - tion).current capability selection the pulser features current drive capability selection. two control inputs (tcc0, tcc1) control the current drive capability (table 2).this feature can be used to save power when working in low voltage mode (such as cwd application) and the maximum current capability is no longer required. MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 43 downloaded from: http:///
sync feature the devices provide the ability to resynchronize all the data inputs by means of a clean clock signal. in ultrasound systems, the fpga output signals are often affected by a high jitter. the jitter induces phase noise that is detrimental in doppler analysis. the input clock can be either a differential signal or a single-ended signal running up to 160mhz. data are clocked in on the rising edge of the tclk+ input (falling edge of tclk-). connect tclk- to gnd for single-ended operation. the sync feature can be enabled or disabled by the tsync control input. drive tsync input low to disable the synchronization func - tion (no external clock signal). drive tsync input high to enable the synchronization function (with an external clock signal). figure 8 shows the simplified tclk+ and tclk- inputs schematic. t/r switch and control each channel features a low-power t/r switch. the t/r switch recovery time after the transmission is less than 1.2s. the t/r switches are controlled by the same puls - er digital inputs (see table 1). no dedicated input signals are required to activate/deactivate the t/r switches. the integrated t/r switches do not require any special timings and can operate synchronously with the digital pulser. in order to minimize the leakage current during transmis - sion, its recommended to switch off the t/r switches 3s before the beginning of the transmit burst. grass clipping diodes a pair of diodes in antiparallel configuration (referred to as grass-clipping diodes) is presented at each pulsers output. the diodes reverse capacitance is extremely low, allowing a perfect isolation between the receive path and the actual pulsers output stage. table 1. transmit pulser operating modes and truth table table 2. transmit pulser output current mode inputs operating mode inputs outputs tmode0 tmode1 tinn_ tipp_ tr_ inb_ (lna input) 0 0 shutdown x high impedance high impedance (t/r switch off) 1 0 octal 3 levels 0 0 clamp on (damp off) gnd (t/r switch off) 1 0 v tvnna /v tvnnb (damp off) gnd (t/r switch off) 0 1 v tvppa /v tvppb (damp off) gnd (t/r switch off) 1 1 clamp on (damp on) t/r switch on 0 1 reserved do not use 1 1 transmit disable 0 0 high impedance (damp off) gnd (t/r switch off) 1 0 high impedance (damp off) gnd (t/r switch off) 0 1 high impedance (damp off) gnd (t/r switch off) 1 1 high impedance (damp on) t/r switch on tcc0 tcc1 pulser output current (typ) 0 0 2a 1 0 1.5a 0 1 1a 1 1 0.5a MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 44 downloaded from: http:///
active damp circuitan active damp circuit is integrated between the internal pulser output node (before grass-clipping diodes) and gnd. the purpose of this circuit is to fully discharge the pulser output internal node so that the node is not left in high-impedance condition as soon as the transmit burst is over. this results in two main advantages 1) the grass-clipping isolation is more effective 2) suppression of any low frequency oscillation of such a node that could be detrimental for doppler mode performances independent (floating) power-supply enable (ten) the device features the ten control input to enable/dis - able the internal fpss. this allows the usage of external high-efficiency power supplies to save system power. this option must be considered only for special applications requiring extremely low power dissipation. the low-power dissipation of the embedded fpss already meets power requirements in most of the cases. drive ten low or leave unconnected to enable the internal fpss; drive ten high to disable the internal fpss. thermal protection the devices feature an open-drain thermal-protection output (thp). when the internal junction temperature exceeds +145c, the devices automatically enter shut - down mode and thp asserts. the devices reenter normal operation and the thp deasserts when the die tempera - ture drops below +125c. analog front end (afe) modes of operation operating modes for the afe are controlled by seventeen 8-bit registers (00hC10h). this is described in the register settings section. low-noise ampliier (lna) each of the devices lnas is optimized for excellent dynamic range and linearity performance characteristics, making it ideal for ultrasound imaging applications. when the lna is placed in low-gain mode, the input resistance (r in ), being a function of the gain a (r in = rf/(1 + a)), increases by a factor of approximately 2. consequently, the switches that control the feedback resistance (r fb ) have to be changed. for instance, the 100? mode in high gain becomes the 200? mode in low gain (table 32) variable-gain ampliier (vga) the devices vgas are optimized for high linearity, high dynamic range, and low output-noise performance, all of which are critical parameters for ultrasound imaging appli - cations. each vga path includes circuitry for adjusting analog gain, as well as an output buffer with differential output ports that drive the aaf and adc. the vga gain can be adjusted through the differential gain-control input (gc+ and gc-). set the differential gain control input volt - age at -3v for minimum gain and +3v for maximum gain. the differential analog control common-mode voltage is 1.65v (typ). figure 8. simplified clock input schematic differential to single-ended conversion single-ended clock select 2:1 mux t vdd 2.5k i 2.5k i 40k i 40k i t clk- reference voltage t clk+ t vcc t vcc t vcc MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 45 downloaded from: http:///
overload recovery the device is also optimized for quick overload recovery for operation under the large input-signal conditions that are typically found in ultrasound input-buffer imaging applications. see the typical operating characteristics for an illustration of the rapid recovery time from a trans - mit-related overload. dynamic offsets or dc offsets in the device can be removed by enabling the digital hpf function contained within the adc. the unique structure of the digital hpf allows for the removal of up to 117mv of dynamic or static dc offset, without reducing the dynamic range of the adc. octal continuous-wave (cw) mixer the device cw mixers are designed using an active dou - ble-balanced topology. the mixers achieve high dynamic range and high-linearity performance, with exceptionally low thermal and jitter noise, ideal for ultrasound cwd signal reception. the octal array exhibits quadrature and in-phase differen - tial current outputs (cq+, cq-, ci+, ci-) to produce the total cwd beamformed signal. the maximum differential current output is typically 3map-p and the mixer output- compliance voltage ranges from 4.5v to 12v. each mixer can be programmed to 1 of 16 phases; there - fore, 4 bits are required for each channel for programming. each cw channel can be programmed to an off state by setting bit cw_shdn_chn to 1. the power-down mode (shdn) line overrides this soft shutdown. after the serial shift registers have been programmed, the cs signal, when going high, loads the phase informa - tion in the form of 5 bits per channel into the i/q phase divider/selectors. this presets the dividers, selecting the appropriate mixer phasing. see table 42 for mixer phase configurations. cw mixer output summation the outputs from the octal-channel mixer array are summed internally to produce the total cwd summed beamformed signal. the octal array produces eight dif - ferential quadrature (q) outputs and eight differential in-phase (i) outputs. all quadrature and in-phase outputs are summed into single i and q differential current outputs (cq+, cq-, ci+, ci-). cwd beamforming is achieved using a single 8 x lo high-frequency master clock that is divided down to the cwd frequency using internal dividers. the beamformer provides /16 resolution with an 8 x lo clock using both edges of the clock, assuming a 50% duty cycle. an eas - ily available low-phase-noise 200mhz master clock can therefore be used to generate the necessary cwd fre - quencies with adequate resolution. lo phase select the lo phase dividers can be programmed through the shift registers to allow for 16 quadrature phases for a complete cw beamforming solution. vga and cw mixer operation during normal operation, the device is configured so that either the vga path is enabled while the mixer array is powered down (vga mode), or the quadrature mixer array is enabled while the vga path is powered down (cw mode). for vga mode, set cwd to a logic-high, and for cw mode, set cwd to a logic-low. external voltage reference connect an external, low-noise, 2.5v reference to the v ref pin. bypass v ref to ground with a 0.1f capaci - tor as close as possible to the device. the device noise performance is dependent on the external noise at v ref . adc clock input the input clock interface provides for flexibility in the requirements of the clock driver. the device accepts a fully differential clock or single-ended logic-level clock (figure 11). the device is specified for an input sam - pling 25mhz to 50mhz frequency range. by default, the internal phase-locked loop (pll) is configured to accept input clock frequencies from 39mhz to 50mhz. the pll is programmed through the pll sampling rate register (00h, table 6). table 7 details the complete range of pll sampling frequency settings. for differential clock operation, connect a differential clock to the clkin+ and clkin- inputs. the input common mode is established internally to allow for ac-coupling. the self-biased input common-mode voltage defaults to 1.2v. the differential clock signal can also be dc-coupled if the externally established common-mode voltage is constrained to the specified clock input common-mode range of 1v to 1.4v. a differential input termination of 100 can be switched in by programming the clkin control register (04h[4], table 21). for single-ended operation, connect clkin- to gnd and drive the clkin+ input with a logic-level signal. when the clkin- input is grounded (or pulled below the threshold of the clock-mode detection comparator), the differential-to- single-ended conversion stage is disabled and the logic- level inverter path is activated. the input common-mode self-bias is disconnected from clkin+, and provides a weak pullup bias to avdd for clkin-. MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 46 downloaded from: http:///
figure 9. cwd analog front-end beamformer simplified block diagram figure 10. cwd output beamforming example i q channel 1 i/q phase divider/ selector 5 loon lo- lo+ cwq cwi clk din ld channel 2 i/q phase divider/ selector channel 3 i/q phase divider/ selector channel 4 i/q phase divider/ selector channel 5 i/q phase divider/ selector channel 6 i/q phase divider/ selector channel 7 i/q phase divider/ selector channel 8 i/q phase divider/ selector i q i q i q i q i q i q i q 5 5 5 5 5 5 5 MAX2082 5-bit sr in out 5-bit sr in out 5-bit sr in out 5-bit sr in out 5-bit sr in out 5-bit sr in out 5-bit sr in out in out 5-bit sr cw_iout+cw_iout- cw_qout- cw_qout+ +v+v lo divider to i channel cwd adc to q channel cwd adc cwd i channels in cwd q channels in cwd i/q lo MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 47 downloaded from: http:///
power-down and low-power mode the device can also be powered down with the shdn pin. set shdn to 1.8v to place the device in power-down mode. in power-down mode, the device draws a total sup - ply current less than 0a from the 5v and 3.3v supplies and less than 0.4ma from the 1.8v supplies. set shdn to logic-low for normal operation. a low-power mode is available to lower the required power for cwd operation. when selected, the complex mixers operate at lower quiescent currents. note that operation in this mode slightly reduces the dynamic per - formance of the device. table 8 shows the logic function of the standard operating modes. in addition to power-down mode, the device can be placed into a reduced-power standby or nap mode, which allows for rapid power-up in vga mode. nap mode is accessible by setting the shdn pin to 1.8v, with the adc_nap_shdn1 and afe_nap_shdn1 registers set to 1 (see table 8). nap mode is not meant to be used in conjunction with cwd mode; valid cwd power states are normal cwd low-power and power-down modes. although no device damage occurs, programming the device for nap mode and setting the shdn pin high can create invalid signal outputs in cwd mode. programmable, digital highpass 2-pole filter digital highpass filter characteristics this digital hpf is implemented as the cascade of two identical first-order highpass iir filter sections (figure 12). each section implements the difference equation: y[n] = r x y[n-1] + x[n] C x[n-1] where x[n] is the input and y[n] is the output. the highpass 3db corner frequency is established by the filter coefficient (r). each section can be independently programmed to one of 10 possible values or placed into bypass mode (table 24). the available filter coefficient values and cor - responding cutoff frequency are given in table 3. figure 11. simplified clock input schematic clkin+ select threshold avdd 10k i 20k i 5k i 5k i 50 i 50 i clkin- input common-mode self-bias block clkin_internal 100 i termination, programmed: 0 differential-to-single-ended clock conversion single-ended clock mode: inverter path select 2:1 mu differential mode: clkin- select threshold single-ended mode: clkin- select threshold MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 48 downloaded from: http:///
figure 12. two-stage digital highpass filter with 1-stage multiplier table 3. digital filter cutoff-frequency setting (bypass) hpf1control bits r1 t hpf1 [3:0] t (bypass) hpf2 r2 t hpf2 [3:0] t g1 atten [1:0] filter coefficient (r) 3db cutoff frequency(f s /2) 3db cutoff frequencymhz (f s = 50msps) one-filter sections 54/64 0.843750 0.046294 1.157 55/64 0.859375 0.041943 1.049 56/64 0.875000 0.037535 0.938 57/64 0.890625 0.033069 0.827 58/64 0.906250 0.028544 0.714 59/64 0.921875 0.023956 0.599 60/64 0.937500 0.019303 0.483 61/64 0.953125 0.014584 0.365 62/64 0.968750 0.009796 0.245 63/64 0.984375 0.004935 0.123 two-filter sections 54/64 0.843750 0.069441 1.736 55/64 0.859375 0.062915 1.573 56/64 0.875000 0.056303 1.408 57/64 0.890625 0.049604 1.240 58/64 0.906250 0.042816 1.070 59/64 0.921875 0.035934 0.898 60/64 0.937500 0.028955 0.724 61/64 0.953125 0.021876 0.547 62/64 0.968750 0.014694 0.367 63/64 0.984375 0.007403 0.185 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 49 downloaded from: http:///
the digital hpf provides a small-signal gain that depends on the filter coefficient. this effectively reduces slightly the full-scale input range of the adc. a plot of filter gain vs. filter coefficient is shown in figure 25. a coarse digital multiplier is incorporated at the output of the filter to pro - vide partial compensation of the digital filter gain. table 4 provides the recommended gain-compensation settings for different filter cutoff-frequency settings. the digital filter magnitude, phase, group-delay, and impulse-time response for 1-stage and 2-stage configu - rations are shown in figure 13 to figure 24, respectively. table 4. gain-compensation settings for different filter cutoff-frequency settings *parts are factory trimmed with this setting. programming can be changed. r filter mode poles f 3db (f s /2) gain gain (db) gain comp (db) overall gain (db) n/a bypass n/a n/a 1 0 0 0 63/64 filter 1 0.004935 1 0.0681 0 0.0681 62/64 filter 1 0.009796 1 0.1368 0 0.1368 61/64 filter 1 0.014584 1 0.206 0 0.206 60/64 filter 1 0.019303 1 0.2758 0 0.2758 59/64 filter 1 0.023956 1 0.3461 0 0.3461 58/64 filter 1 0.028544 15/16 0.417 -0.5606 -0.1436 57/64 filter 1 0.033069 15/16 0.4885 -0.5606 -0.0721 56/64 filter 1 0.037535 15/16 0.5606 -0.5606 0 55/64 filter 1 0.041943 15/16 0.6333 -0.5606 0.0727 54/64 filter 1 0.046294 15/16 0.7066 -0.5606 0.146 63/64 filter 2 0.007403 1 0.1362 0 0.1362 62/64 filter 2 0.014694 1 0.2736 0 0.2736 61/64 filter 2 0.021876 15/16 0.412 -0.5606 -0.1486 60/64* filter 2 0.028955 15/16 0.5515 -0.5606 -0.0091 59/64 filter 2 0.035934 15/16 0.6922 -0.5606 0.1316 58/64 filter 2 0.042816 15/16 0.834 -0.5606 0.2734 57/64 filter 2 0.049604 7/8 0.977 -1.1598 -0.1828 56/64 filter 2 0.056303 7/8 1.1211 -1.1598 -0.0387 55/64 filter 2 0.062915 7/8 1.2665 -1.1598 0.1067 54/64 filter 2 0.069441 7/8 1.4131 -1.1598 0.2533 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 50 downloaded from: http:///
figure 13. digital hpf magnitude frequency response (1 stage) figure 15. digital hpf phase response (1 stage) figure 16. digital hpf group-delay frequency response (1 stage) figure 14. digital hpf magnitude frequency response (1 stage) at corner frequency digital hpf group-delay frequency response (2 stage) frequency (normalized f s /2) delay (samples) 10 -1 10 -2 1 2 3 4 5 6 7 10 0 10 -3 10 0 r1 r2 54/64 r1 r2 63/64 digital hpf magnitude frequency response (1 stage) frequency (normalized f s /2) response (db) 10 -1 10 -2 -6 -5 -4 - -2 -1 0 1 2 - 10 - 10 0 digital hpf phase frequency response (1 stage) frequency (normalized f s /2) phase ( ) 10 -1 10 -2 20 40 60 80 100 120 140 160 180 0 10 - 10 -0 r1 4/64 r1 6/64 digital hpf group-delay frequency response (1 stage) frequency (normalized f s /2) delay (samples) 10 -1 10 -2 1 2 3 4 5 6 7 10 0 10 -3 10 0 r1 54/64 r1 63/64 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 51 downloaded from: http:///
figure 17. digital hpf impulse-time response (1 stage) figure 19. digital hpf magnitude frequency response (2 stage) figure 20. digital hpf magnitude frequency response (2 stage) at corner frequency figure 18. digital hpf impulse-time response detailed plot (1 stage) digital hpf impulse-time response (1 stage) time (samples) response 160 140 0 20 40 80 100 60 120 -0.2 0 0.2 0.4 0.6 0.8 1.0 -0.4 -20 180 digital hpf impulse-time response (1 stage) time (samples) response 45 40 30 35 10 15 20 25 5 -0.25 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0 50 r1 = 63/64 r1 = 54/64 frequency (normalized f s /2) response (db) 10 -1 10 -2 10 -3 10 0 digital hpf magnitude-frequency response (2 stage) -40 -30 -20 -10 0 10 -50 r1 3/4 r1 54/4 digital hpf magnitude-frequency response (2 stage) frequency (normalized f s /2) response (db) 10 -1 10 -2 -6 -5 -4 - -2 -1 0 1 2 - 10 - 10 0 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 52 downloaded from: http:///
figure 21. digital hpf phase response (2 stage) figure 23. digital hpf impulse-time response (2 stage) figure 24. digital hpf impulse-time response detailed plot (2 stage) figure 22. digital hpf group-delay frequency response (2 stage) digital hpf phase frequency response (2 stage) frequency (normalized f s /2) phase (degrees) 10 -1 10 -2 20 40 60 80 100 120 140 160 180 0 10 - 10 0 r1 4/64 r1 6/64 digital hpf group-delay frequency response (2 stage) frequency (normalized f s /2) delay (samples) 10 -1 10 -2 1 2 3 4 5 6 7 10 0 10 -3 10 0 r1 r2 54/64 r1 r2 63/64 digital hpf impulse-time response (2 stage) time (samples) response 140 120 0 20 40 80 60 100 -0.2 0 0.2 0.4 0.6 0.8 1.0 -0.4 -20 180 160 digital hpf impulse-time response (2 stage) time (samples) response 45 40 30 35 10 15 20 25 5 -0.25 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0 50 r1 = r2 = 54/64 r1 = r2 = 63/64 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 53 downloaded from: http:///
system timing requirements figure 26 shows the relationship between the analog inputs, input clock, frame-alignment output, serial-clock output, and serial-data outputs. the differential adc input signal is sampled on the rising edge of the applied clock signal (clkin+, clkin-), and the resulting data appears at the digital outputs 10.5 clock cycles later. figure 27 provides a detailed, two-conversion timing diagram of the relationship between inputs and outputs. clock output (clkout+, clkout-) the adc provides a differential clock output that consists of clkout+ and clkout-. as shown in figure 28, the serial-output data is clocked out of the device on both edges of the clock output. the frequency of the output clock is six times (6x) the frequency of the input clock. the output data format and test pattern/digital hpf select register (01h) allows the phase of the clock output to be adjusted relative to the output data frame (table 9, figure 30). figure 25. digital hpf gain vs. filter coefficient figure 26. adc timing (overall) digital hpf gain vs. filter coefficient filter coefficient (/64) gain (db) 62 60 58 56 54 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 52 64 + + + + + + + + + ++ + + + + + + + + + 2-stage iir 1-stage iir in_+ - in_- clkin+ - clkin- clkout+ - clkout- out_+ - out_- frame+ - frame- t sample n - 10 n - 9 n - 8 n - 7 n - 6 n - 5 n - 4 n - 3 n - 2 n - 1 n output data frame n n + 1 n + 2 n + 3 n + 4 n + 5 105 clock-ccle data latenc n + 6 n + 7 n + 8 n + 9 n + 10 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 54 downloaded from: http:///
frame-alignment output (frame+, frame-) the adc provides a differential frame-alignment signal that consists of frame+ and frame-. as shown in figure 27, the rising edge of the frame-alignment signal corresponds to the first bit (d0) of the 12-bit serial-data stream. the frequency of the frame-alignment signal is identical to the frequency of the input clock; however, the duty cycle varies depending on the input clock frequency. serial-output data (out_+, out_-) the adc provides conversion results through individual differential outputs consisting of out_+ and out_-. the results are valid 10.5 input clock cycles after a sample is taken. as shown in figure 28, the output data is clocked out on both edges of the output clock, lsb (d0) first (by default). figure 27 displays the detailed serial-output tim - ing diagram. differential lvds digital outputs the adc features programmable, fully differential lvds digital outputs. by default, the 12-bit data output is trans - mitted lsb first, in offset binary format. the output data format and test pattern/digital hpf select register (01h, table 9) allows customization of the output bit order and data format. the output bit order can be reconfigured to transmit msb first, and the output data format can be changed to twos complement. table 10 contains full out - put data configuration details. the lvds outputs feature flexible programming options. first, the output common-mode voltage can be pro - grammed from 0.6v to 1.2v (default) in 200mv steps (table 17). use the lvds output driver level register (02h, table 13) to adjust the output common-mode voltage. the lvds output driver current is also fully programmable through the lvds output driver management register (03h, table 18). by default, the output driver current is set to 3.5ma. the output driver current can be adjusted from 0.5ma to 7.5ma in 0.5ma steps (table 19). the lvds output drivers also feature optional internal ter - minations that can be enabled and adjusted by the lvds output driver management register (03h, table 18). by default, the internal output driver termination is disabled. see table 20 for all possible configurations. figure 27. adc timing (detail) figure 28. serial output detailed timing diagram t sample t sf t df n n + 1 d7 n-9 d0 n-8 d11 n-9 d10 n-9 d1 n-8 d2 n-8 d3 n-8 d4 n-8 d5 n-8 d6 n-8 d7 n-8 d8 n-8 d9 n-8 d10 n-8 d11 n-8 d9 n-9 d8 n-9 d0 n-7 d1 n-9 d2 n-9 d3 n-9 d4 n-9 d5 n-9 d6 n-9 in_+ - in_- clkin+ - clkin- clkout+ - clkout- out_+ - out_- frame+ - frame- t sample sample period t df frame_ rise to clkout_ rise t sf sample clkin_ rise to frame rise t od t ch t od d0 d1 d2 d3 d4 t cl clkout+ - clkout- out_+ - out_- t ch clkout_ output- width high t cl clkout_ output- width low t od data valid to clkout_ rise/fall MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 55 downloaded from: http:///
output driver level tests the lvds outputs (data, clock, and frame) can be con - figured to static logic-level test states through the lvds output driver level register (02h, table 13). the com - plete list of settings for the static logic-level test states can be found in table 14 to table 16. data output test patterns the lvds data outputs can be configured to output sev - eral different, recognizable test patterns. test patterns are enabled and selected using the output data format and test pattern/digital hpf select register (01h, table 9). a complete list of test pattern options are listed in table 11, and custom test pattern details can be found in the cus - tom test pattern registers (07h, 08h, 09h) section (includ - ing table 26, table 29, and table 30). power management the shdn input is used to toggle between two power- management states. power state 0 corresponds to shdn = 0, while power state 1 corresponds to shdn = 1. the pll sampling rate and power management register (00h, table 6) and the channel power management reg - isters (05h and 06h, table 22 and table 23) fully define each power-management state. by default, shdn = 1 shuts down the device, and shdn = 0 returns the adcs to full-power operation. use of the shdn input is not required for power management. for either state of shdn, complete power-management flexibility is provided, including individual adc channel power-management control, as well as the option of which reduced power-mode to utilize in each power state. the reduced-power modes available are sleep mode and nap mode. the device cannot enter either of these states unless no adc channels are active in the current power state (table 8). in nap mode, the reference, duty-cycle equalizer, and clock-multiplier pll circuits remain active for rapid wake - up time. in nap mode, the externally applied clock signal must remain active for the duty-cycle equalizer and pll to remain locked. typical wake-up time from nap mode is 2s. in sleep mode, all circuits are turned off except for the bandgap voltage-generation circuit. all registers retain previously programmed values during sleep mode. typical wakeup time from sleep mode is 2ms (typ). power-on and reset the user-programmable register default settings and other factory-programmed settings are stored in a non - volatile memory. upon device power-up, these values are loaded into the control registers. the operation occurs after the application of a valid supply voltage to avdd and ovdd, and the presence of an input clock signal. the user-programmed register values are retained as long as the avdd and ovdd voltages are applied. a reset condition overwrites all user-programmed regis - ters with the factory-default values. the reset condition occurs on power-up and can be initiated while powered with a software write command (write 5ah) through the serial-port interface to the special function register (10h). the reset time is proportional to the adc clock period and requires 415s at 50msps. power-down and low-power (nap) mode and channel selection the shdn pin is a toggle switch between any two power-management states. in most cases, the shdn = 0 state is on, and the shdn = 1 state is off. however, complete flexibility is provided, allowing the user to toggle between active and nap, active and sleep, etc. nap mode is defined as a reduced-power state with rapid wake-up time on the order of 2s. sleep mode is a very-low-power mode (~1mw) with a much longer wake-up time on the order of 2ms. the serial port and programmable registers remain active during nap and sleep modes. chn_on_shdn0 n = [1:8] 1 channel n is on when the shdn pin is low. 0 channel n is off when the shdn pin is low. chn_on_shdn1 n = [1:8] 1 channel n is on when the shdn pin is high. 0 channel n is off when the shdn pin is high. MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 56 downloaded from: http:///
adc_nap_shdn0 1 adc in nap mode when all channels are off, or the cwd pin is high and the shdn pin is low. 0 adc in sleep mode when all channels are off, or the cwd pin is high and the shdn pin is low. adc_nap_shdn1 1 adc in nap mode when all channels are off, or the cwd pin is high and the shdn pin is high. 0 adc in sleep mode when all channels are off, or the cwd pin is high and the shdn pin is high. afe_nap_shdn0 1 afe in nap mode when all channels are off and the shdn pin is low. 0 afe in sleep mode when all channels are off and the shdn pin is low. afe_nap_shdn1 1 afe in nap mode when all channels are off and the shdn pin is high. 0 afe in sleep mode when all channels are off and the shdn pin is high. 3-wire serial peripheral interface (spi) the adc operates as a slave device that sends and receives data through a 3-wire spi interface. a master device must initiate all data transfers to and from the device. the device uses an active-low spi chip-select input ( cs ) to enable communication with timing controlled through the externally generated spl clock input (sclk). all data is sent and received through the bidirectional spi data line (sdio). the device has 16 user-programmable control registers and one special-function register, which are accessed and programmed through this interface. spi communication format figure 29 shows an adc spi communication cycle. all spi communication cycles are made up of 2 bytes of data on sdio and require 16 clock cycles on sclk to be completed. to initiate an spi read or write communication cycle, cs must first transition from a logic-high to a logic- low state. while cs remains low, serial data is clocked in from sdio on rising edges of sclk, and clocked out (for a read) on the falling edges of sclk. when cs is high, the device does not respond to sclk transitions, and no data is read from or written to sdio. cs must transition back to logic-high after each read/write cycle is completed. the first byte transmitted on sdio is always provided by the master. the adc (slave device) clocks in the data from sdio on each rising edge of sclk. the first bit received selects whether the communication cycle is a read or a write. logic 1 selects a read cycle, while logic 0 selects a write cycle. the next 7 bits (msb first) are the register address for the read or write cycle. the address can indicate any of the 16 user-programmable control registers (00h to 0fh), or the special-function register (10h, write only). attempting to read/write with any other address has no effect (table 3). the second byte on sdio is sent to the adc in the case of a write, or received from the adc in the case of a read. for a write command, the device continues to clock in the data on sdio on each rising edge of sclk. in the case of a read command, the device writes data to sdio on each falling edge of sclk. the data byte is transmitted and received msb first in both cases. the detailed spi timing requirements are shown in figure 29. output clock phase clkout_phase[1:0] default por is 00. see figure 30 for various output clock phase configurations. MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 57 downloaded from: http:///
figure 29. spi timing diagram t css t csh t sclk t sds t sdh t sdd cs sclk sdio cs sclk sdio r/w a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 write address data write or read read t sclk sclk period t css sclk-to-cs setup time t csh sclk-to-cs hold time t sds sdio-to-sclk setup time t sdh sdio-to-sclk hold time t sdd sclk-to-sdio output data delay r / w 0 = write 1 = read MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 58 downloaded from: http:///
table 5. user-programmable adc control registers table 6. pll sampling rate and power management (00h) table 7. pll frequency-control settings (00h[6:4]) x = dont care. address read/write por state function 00h r/w 0001 0001 pll sampling rate and power management 01h r/w 0000 0000 output data format and test pattern/digital hpf select 02h r/w 0000 0000 lvds output driver level 03h r/w 0000 0000 lvds output driver management 04h r/w 0000 0000 adc clkin control 05h r/w 1111 1111 channel power management: shdn0 06h r/w 0000 0000 channel power management: shdn1 07h r/w 0100 0100 digital hpf 1 and 2: -3db cutoff/custom test patterns 1 08h r/w 0101 0110 digital hpf 1 and 2: atenuation/custom test patterns 2 09h r/w 0101 1010 custom test patterns 2 and 1 (4 most signiicant bits) 0ah r/w 0101 1100 afe settings 0bh r/w 0000 0000 cw beamformer 1 0ch r/w 0000 0000 cw beamformer 2 0dh r/w 0000 0000 cw beamformer 3 0eh r/w 0000 0000 cw beamformer 4 0fh r/w 0000 0000 cw beamformer 5 10h r/w n/a special function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pll[2:0] afe_nap_shdn1 afe_nap_shdn0 adc_nap_shdn1 adc_nap_shdn0 clock multiplier setting minimum sampling frequency (mhz) maximum sampling frequency (mhz) pll[2] pll[1] pll[0] 0 0 0 not used 0 0 1 39 50 0 1 0 28.5 39 0 1 1 25 28.8 1 x x not used MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 59 downloaded from: http:///
table 8. power-management programming x = dont care. table 9. output data format and test pattern/digital hpf select (01h) pins registers description shdn cwd chn_on_shdn0 n = [1:8] chn_on_shdn1 n = [1:8] adc_nap_shdn0adc_nap_shdn1 afe_nap_shdn0afe_nap_shdn1 default register modes 0 0 11111111 00000000 0 1 0 1 8 channels active (vga mode) 0 1 11111111 00000000 0 1 0 1 cw doppler mode (adc in nap mode) 1 0 11111111 00000000 0 1 0 1 nap mode (adc and afe) 1 1 11111111 00000000 0 1 0 1 cw doppler mode (adc in nap mode) programmed register modes 0 0 not all zero xxxxxxxx x x x x 1 or more channels active (vga mode) 0 0 00000000 xxxxxxxx 0 x 0 x sleep mode (adc and afe) 0 0 00000000 xxxxxxxx 0 x 1 x adc sleep/afe nap 0 0 00000000 xxxxxxxx 1 x 0 x adc nap/afe sleep 0 0 00000000 xxxxxxxx 1 x 1 x nap mode (adc and afe) 0 1 xxxxxxxx xxxxxxxx 0 x x x cw doppler mode (adc in sleep mode) 0 1 xxxxxxxx xxxxxxxx 1 x x x cw doppler mode (adc in nap mode) 1 0 xxxxxxxx not all zero x x x x 1 or more channels active (vga mode) 1 0 xxxxxxxx 00000000 x 0 x 0 sleep mode (adc and afe) 1 0 xxxxxxxx 00000000 x 0 x 1 adc sleep/afe nap 1 0 xxxxxxxx 00000000 x 1 x 0 adc nap/afe sleep 1 0 xxxxxxxx 00000000 x 1 x 1 nap mode (adc and afe) 1 1 xxxxxxxx xxxxxxxx x 0 x x cw doppler mode (adc in sleep mode) 1 1 xxxxxxxx xxxxxxxx x 1 x x cw doppler mode (adc in nap mode) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 test_pattern[2:0] test_data clkout_phase[1:0] data_format bit_order MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 60 downloaded from: http:///
custom test pattern when custom test pattern is selected (test_pattern[2:0] = 010), the output alternates between bits_custom1[11:0] and bits_custom2[11:0]. if a single repeating word is desired, program bits_custom2[11:0] to the same value as bits_custom1[11:0]. table 10. lvds output data format programming (01h[1:0]) table 11. test pattern programming and digital highpass filter selection figure 30. output clock phase x = dont care. data_format bit_order lvds output data format 0 0 offset binary, lsb irst (default 0 1 offset binary, msb irst 1 0 twos complement, lsb irst 1 1 twos complement, msb irst c lk out c lk out datadata d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 frame clkout datadata frame clkout frame frame clkout_phase [1:0] = 00 (default) clkout_phase [1:0] = 10 clkout_phase [1:0] = 01 clkout_phase [1:0] = 11 d0 d1 d2 d3 test_data test_pattern[2:0] test pattern format 0 x x x disabled, normal operation with digital hpf selected (default) 1 0 0 0 data skew (010101010101), repeats every frame 1 0 0 1 data sync (111111000000), repeats every frame 1 0 1 0 custom test pattern, repeats every 2 frames 1 0 1 1 ramping pattern from 0 to 4095 (repeats) 1 1 0 0 pseudorandom data pattern, short sequence (2 9 ) 1 1 0 1 pseudorandom data pattern, long sequence (2 23 ) 1 1 1 x not used MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 61 downloaded from: http:///
table 12. pseudorandom data test pattern table 13. lvds output driver level (02h) table 14. test data (out_) level programming table 15. test clkout_ level programming table 16. test frame level programming table 17. lvds output common-mode voltage adjustment note: when custom test pattern is selected (test_pattern[2:0] = 100) the output is a short (2 9 ) pn sequence. a long (2 23 ) sequence output is provided when test_pattern[2:0] = 101. x = dont care. x = dont care. x = dont care. sequence initial value first 3 samples short (2 9 ) 0x0df 0xdf9, 0x353, 0x301 long (2 23 ) 0x29b80a 0x591, 0xfd7, 0x0a3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lvds_cm[1:0] test_frame_level[1:0] test_clkout_level[1:0] test_data_level[1:0] test_data_level[1:0] data (out_) output x 0 normal data output 0 1 output low (static) 1 1 output high (static) test_clkout_level[1:0] clkout_ output x 0 normal clkout_ output 0 1 output low (static) 1 1 output high (static) test_frame_level[1:0] frame output x 0 normal frame output 0 1 output low (static) 1 1 output high (static) lvds_cm[1:0] lvds output common-mode voltage (v) 0 0 1.2 (default) 0 1 1.0 1 0 0.8 1 1 0.6 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 62 downloaded from: http:///
table 18. lvds output driver management (03h) table 19. lvds output drive current configuration table 20. lvds output driver internal termination configuration table 21. clkin termination control (04h) note: selectable lvds drive current fully selectable from 0.5ma to 7.5ma in 0.5ma increments (3.5ma default). supports ansi-644 and ieee 1596.3. always program this bit to 0. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lvds_term[2:0] lvds_iadj[3:0] lvds_iadj[3:0] lvds current (ma) 0 0 0 0 3.5ma, 350mv at 100 w (default) 0 0 0 1 0.5 0 0 1 0 1.0 0 0 1 1 1.5 0 1 0 0 2.0 0 1 0 1 2.5 0 1 1 0 3.0 0 1 1 1 3.5 1 0 0 0 4.0 1 0 0 1 4.5 1 0 1 0 5.0 1 0 1 1 5.5 1 1 0 0 6.0 1 1 0 1 6.5 1 1 1 0 7.0 1 1 1 1 7.5 lvds_term[2:0] lvds internal termination () 0 0 0 0 0 1 800 0 1 0 400 0 1 1 267 1 0 0 200 1 0 1 160 1 1 0 133 1 1 1 100 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clkin_term 0* MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 63 downloaded from: http:///
clock input termination clkin_term = 0: 100 not selected. clkin_term = 1: switches in 100 across differential clock inputs. table 22. channel power management: shdn0 (05h) table 23. channel power management: shdn1 (06h) table 24. digital highpass filter control coefficients (07h; if test_data 01[4]) = 0) table 25. digital highpass filter configuration table 26. custom test pattern 1 (07h; if test_data 01[4]) = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ch8_shdn0 ch7_shdn0 ch6_shdn0 ch5_shdn0 ch4_shdn0 ch3_shdn0 ch2_shdn0 ch1_shdn0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ch8_shdn1 ch7_shdn1 ch6_shdn1 ch5_shdn1 ch4_shdn1 ch3_shdn1 ch2_shdn1 ch1_shdn1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hpf2[3:0] hpf1[3:0] hpf1[3:0], hpf2[3:0] r1/r2 filter mode 0 0 0 0 n/a bypass 0 0 0 1 63/64 filter; f 3db = 0.004935, f s /2 0 0 1 0 62/64 filter; f 3db = 0.009796, f s /2 0 0 1 1 61/64 filter; f 3db = 0.014584, f s /2 0 1 0 0 60/64 filter; f 3db = 0.019303, f s /2 0 1 0 1 59/64 filter; f 3db = 0.023956, f s /2 0 1 1 0 58/64 filter; f 3db = 0.028544, f s /2 0 1 1 1 57/64 filter; f 3db = 0.033069, f s /2 1 0 0 0 56/64 filter; f 3db = 0.037535, f s /2 1 0 0 1 55/64 filter; f 3db = 0.041943, f s /2 1 0 1 0 54/64 filter; f 3db = 0.046294, f s /2 1 0 1 1 bypass 1 1 0 0 bypass 1 1 0 1 bypass 1 1 1 0 bypass 1 1 1 1 bypass bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bits_custom1[7:0] MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 64 downloaded from: http:///
table 27. digital highpass filter attenuation (08h; if test_data 01[4]) = 0) table 28. digital highpass filter attenuation table 29. custom test pattern 2 (08h; if test_data 01[4]) = 1) table 30. custom test pattern 3 (09h) table 31. afe settings (0ah) table 32. afe input impedance and lna gain control x = dont care. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 aten[1:0] aten[1:0] gain gain (db) 0 0 1 0 0 1 1 0 1 0 15/16 -0.58 1 1 7/8 -1.16 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bits_custom2[7:0] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bits_custom2[11:8] bits_custom1[11:8] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 afe_rin[0:2] afe_lna_gain afe_bw[0:1] cwd_power_mode afe_oclamp afe_lna_gain afe_rin[0:2] input resistance () lna gain (db) 0 0 0 0 100 12.5 0 1 0 0 200 12.5 0 0 1 0 400 12.5 0 1 1 0 1000 12.5 0 x x 1 external r 12.5 1 0 0 0 50 18.5 1 1 0 0 100 18.5 1 0 1 0 200 18.5 1 1 1 0 500 18.5 1 x x 1 external r 18.5 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 65 downloaded from: http:///
table 33. afe aaf filter bandwidth control table 39. cw beamformer 4 (0eh) table 35. vga output clamp control table 37. cw beamformer 2 (0ch) table 34. cwd power mode table 36. cw beamformer 1 (0bh) table 38. cw beamformer 3 (0dh) afe_bw[0:1] bandwidth (mhz) 0 0 9 0 1 10 1 0 15 1 1 18 cwd_power_mode cwd power mode 0 full power (default, nominal) 1 low power afe_oclamp vga output clamp 0 no clamp (default, nominal) 1 clamp active bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cw_phase_ch2[1:3] cw_shdn_ch1 cw_phase_ch1[0:3] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cw_phase_ch4[3] cw_shdn_ch3 cw_phase_ch3[0:3] cw_shdn_ch2 cw_phase_ch2[0] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cw_phase_ch5[0:3] cw_s hdn_ch4 cw_phase_ch4[0:2] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cw_phase_ch7[2:3] cw_shdn_ch6 cw_phase_ch6[0:3] cw_shdn_ch5 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 66 downloaded from: http:///
cw doppler mode control cw_shdn_chn is set to 0 in normal operation (default). set it to 1 for power-down channel n when in cw doppler mode. note: the transfer data to afe procedure described in the afe programming and data transfer section should be per - formed twice when setting any cw_shdn_chn bits from 0 to 1 to enable a cw doppler channel(s). this procedure only applies to the cw_shdn_chn bits; all other bits are transferred to the afe in a single operation. table 41. phase rotation bit weight table 40. cw beamformer 5 (0fh) table 42. phase rotation summary table 43. special function register (10h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cw_shdn_ch8 cw_phase_ch8[0:3] cw_shdn_ch7 cw_phase_ch7[0:1] cw_phase_chn[0:3] phase -22.5 -180 -90 -45 degrees cw_phase_chn[0:3] phase (degrees) -22.5 -180 -90 -45 0 0 0 0 0 0 0 0 1 337.5 0 0 1 0 180 0 0 1 1 157.5 0 1 0 0 270 0 1 0 1 247.5 0 1 1 0 90 0 1 1 1 67.5 1 0 0 0 315 1 0 0 1 292.5 1 0 1 0 135 1 0 1 1 112.5 1 1 0 0 225 1 1 0 1 202.5 1 1 1 0 45 1 1 1 1 22.5 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 status7 status6 status5 status4 status3 status2 status1 status0 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 67 downloaded from: http:///
soft resetsoftware reset allows the user to reset the part through writes to the serial port. a soft reset can be performed by writing the reset code 5ah to address 10h. upon initiation of soft reset, the fuse memory is read and loaded into the spi registers. see the 3-wire serial peripheral interface (spi) section for further detail. the reset is self-clearing, subsequent serial-port write(s) are not needed to clear the reset condition. afe programming and data transfer the internal analog front-end (afe) and adc are pro - grammed through a common serial-port interface. there are 48 user-programmable bits in the adc that store afe control information. these bits are written to registers 0ah to 0fh in the adc, and transferred to the afe shift reg - isters when aeh is written to register 10h. the user must provide at least 50 clock cycles on sclk after this control word is written to complete the data transfer to the afe. to verify that the data has been transferred to the afe, poll address 10h until bit 6 is 0. as a final step, write 00h to address 10h. changes in registers 0ah to 0fh do not take effect in the afe until this transfer is complete. cwd beamformer programming and clocking programming of the cwd beamformer occurs in the fol - lowing sequence: 1) during normal cwd mode, the mixer clock (lo+, lo-) is on. loon is high. 2) shut off the mixer clock (lo+, lo-) or pull loon low to start the programming sequence. 3) write the phase and channel shutdown information into the proper control registers. 4) transfer the phase information from the control regis - ters to the afe (see above) and wait for the write to complete. turn on the mixer clock and set loon to high to start beamforming (the afe shift registers can also be written with the mixer clock running and loon set low). if turning on the mixer clock source, the clock must turn on such that it starts at the beginning of a mixer clock cycle. a narrow glitch on the mixer clock is not acceptable and could cause metastability in the i/q phase dividers. if using the loon control to turn on the mixer clock, the loon signal must be synchro - nous to the lo clock, and it must meet the minimum setup time specification. table 44. status byte (reads from 10h) table 45. spi commands (writes to 10h) note: all commands are issued by writing spi address 10h. status bit no. read value description 7 0 reserved 6 0 1 = afe load in progress; 0 = load complete 5 0 or 1 1 = rom read in progress 4 0 or 1 1 = rom read completed, and register data is valid (checksum ok) 3 0 reserved 2 1 reserved 1 0 or 1 reserved 0 0 or 1 1 = duty-cycle equalizer dll is locked command write data description soft reset 5ah initiates software reset transfer data to afe aeh initiates transfer of data in adc registers 0ah to 0fh to afe MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 68 downloaded from: http:///
5) to program new cwd phase information, turn off the mixer clock and/or set loon low and repeat steps 1C5. 6) for switching between vga and cwd modes without reprogramming the spi registers (fast mode switch - ing): when changing from cwd mode to vga mode, nothing needs to be done to maintain the afe pro - gramming settings. when switching from vga mode to cwd mode, the user must provide a cs pulse after the cwd pin goes high to initialize the cwd beam - former phase registers. this pulse must occur 100ns or more after the rising edge of the cwd pin, and must be at least 80ns in width. applications information layout concerns the device provides several gnd connections under - neath package for improved thermal performance. do not run traces under the package to avoid possible short circuits. to aid heat dissipation, connect gnd to similarly sized pads on the component side of the pcb. these pads should be connected through to the solder-side copper by several plated holes to a large heat-spreading copper area to conduct heat away from the device. the devices high-speed pulser requires low-inductance bypass capacitors to their supply inputs. high-speed pcb trace design practices are recommended. pay particular attention to minimize trace lengths and use sufficient trace width to reduce inductance. use of surface-mount compo - nents is recommended.power-supply sequencing when using the embedded fpss (ten = low), the devic - es do not require any power-up/power-down sequence. when external fpss are used (ten = high), the condi - tions v tvgp_ > (v tvee - 0.6v) and v tvgn_ < (v tvcc + 0.6v) must be satisfied during the entire power-up/ power-down transients (see the electrical characteristics tables). internal esd protection diodes impose certain restrictions on the power-supply sequence. the v cc5 supply should always be greater than the v cc3 supply, otherwise, excessive current can flow and cause damage. the avdd and ovdd supplies are internally connected through anti - parallel diodes and should always be within 0.3v of each other, otherwise, excessive current can flow and cause damage. the 11v supply used to pulll up the ci +/- and cq +/- pins must always be greater than the v cc5 supply, otherwise, excessive current can flow and cause damage. ultasound-speciic imd3 speciication unlike typical communications applications, the two input tones are not equal in magnitude for the ultrasound-spe - cific imd3 two-tone specification. in this measurement, f 1 represents reflections from tissue and f 2 represents reflections from blood. the latter reflections are typically 25db lower in magnitude. im3 performance for the device is measured with the smaller tone at -25dbc in order to more accurately resolve the small im3 products over the thermal noise floor. the imd3 product of interest (f 1 - (f 2 - f 1 )) presents itself as an undesired doppler error signal in ultrasound applications (see figure 31). figure 31. ultrasound-specific imd3 ultrasound imd3 -25db f 1 - (f 2 - f 1 ) f 2 + (f 2 - f 1 ) f 1 f 2 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 69 downloaded from: http:///
+denotes a lead(pb)-free/rohs-compliant package. part temp range pin-package MAX2082cxd+ 0c to +70c 336 csbga package type package code outline no. land pattern no. 336 csbga x336023m+3 21-0639 90-0388 MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer www.maximintegrated.com maxim integrated 70 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bcdmos/bicmos/cmos ordering information downloaded from: http:///
revision number revision date description pages changed 0 9/14 initial release maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. MAX2082 low-power, high-performance octal ultrasound transceiver with integrated afe, pulser, t/r switch, and cwd beamformer ? 2014 maxim integrated products, inc. 71 revision history for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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